Stats

  • Locked Locked
  • Replies 5
  • Subscribers 92
  • Views 2776
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

short circuit problems in P & R

quiet

I'm using layer 3 and layer 4 for the power routing, so there are many vias through layer 3, layer 2 to layer 1.

Then there are some short circuit problems when some signals pass through the vias. Is there any option to avoid this kind of problems? Can't the tool detect these short problems and avoid these?

Thanks.

Parents
  • fitz

    If there is any active circuitry on the cell row I would be very wary of deleting either of the nearest power via stacks completely.
    That may lead to static and / or  dynamic  IR drop  issues, local voltages lower than your worst case timing library will model correctly.
    Finding IR drop problems at the last minute before tape out is no fun whatsoever, believe me.

    You can use the "editPowerVia" command to selectively reduce the array size of the power via stacks in the problem areas.
    For example, reduce the via stack array from a 6x1 array to a 4x1 in localized problem areas.

    Or if you know the "full sized"  power via stack array is over kill for your technology / library / circuit
    you can globally shrink them from the start with  the addStripe option -max_via_size.


    Shawn  

Reply
  • fitz

    If there is any active circuitry on the cell row I would be very wary of deleting either of the nearest power via stacks completely.
    That may lead to static and / or  dynamic  IR drop  issues, local voltages lower than your worst case timing library will model correctly.
    Finding IR drop problems at the last minute before tape out is no fun whatsoever, believe me.

    You can use the "editPowerVia" command to selectively reduce the array size of the power via stacks in the problem areas.
    For example, reduce the via stack array from a 6x1 array to a 4x1 in localized problem areas.

    Or if you know the "full sized"  power via stack array is over kill for your technology / library / circuit
    you can globally shrink them from the start with  the addStripe option -max_via_size.


    Shawn  

Children
No Data

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.