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  3. Power domains or not?

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Power domains or not?

schnufff
schnufff over 12 years ago

Hi all,

I have to setup a chip with 5 completely separated cores. Each core has its own vcc_core/io and vdd_core/io ind i/o pins.

But the actual voltage of all cores is 1.8V. For testing only one core should be active at a time.

Can I do this just with connectGlobalNet or is this more like a multi supply voltage flow with a single volate?

 

If there is some documentation about this topic, please give me a hint. The UserGuide didn't cover this topic.

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  • schnufff
    schnufff over 12 years ago

     Hi Kari, thanks for the reply

    To make it clearer: We are only powering one core via external vcc at a time. There is no need for power switches. The used lib even does not have and power awareness. My problem in the moment is, that the power supply lines of the standard cell rows are always connected to the last used vcc_core$. 

     

    what I have is one toplevel module which instanciates the 5 cores. than i create a fence for each core, create the powerrings around the fence and connect the pin vdd_core (only under module core1) to global net vdd_core1. the same for cores 2 to 5.

     

    how can i restrict sroute to only route the standard cell vdd lanes inside the area of the module fences? outside the fences there will be no logic at all, only wires.

     

    Thanks

    Stefan

     

     

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  • schnufff
    schnufff over 12 years ago

     Hi Kari, thanks for the reply

    To make it clearer: We are only powering one core via external vcc at a time. There is no need for power switches. The used lib even does not have and power awareness. My problem in the moment is, that the power supply lines of the standard cell rows are always connected to the last used vcc_core$. 

     

    what I have is one toplevel module which instanciates the 5 cores. than i create a fence for each core, create the powerrings around the fence and connect the pin vdd_core (only under module core1) to global net vdd_core1. the same for cores 2 to 5.

     

    how can i restrict sroute to only route the standard cell vdd lanes inside the area of the module fences? outside the fences there will be no logic at all, only wires.

     

    Thanks

    Stefan

     

     

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