I have to setup a chip with 5 completely separated cores. Each core has its own vcc_core/io and vdd_core/io ind i/o pins.
But the actual voltage of all cores is 1.8V. For testing only one core should be active at a time.
Can I do this just with connectGlobalNet or is this more like a multi supply voltage flow with a single volate?
If there is some documentation about this topic, please give me a hint. The UserGuide didn't cover this topic.
It almost sounds like you can just use globalNetConnect, but when you say that only one core should be active at a time, that implies domains controlled by power-switch cells, which is more complicated. There is a Low Power Design chapter in the EDI user guide, have you reviewed that? If you need further info, search for Low Power on support.cadence.com. There will be some other documentation there.
Hi Kari, thanks for the reply
To make it clearer: We are only powering one core via external vcc at a time. There is no need for power switches. The used lib even does not have and power awareness. My problem in the moment is, that the power supply lines of the standard cell rows are always connected to the last used vcc_core$.
what I have is one toplevel module which instanciates the 5 cores. than i create a fence for each core, create the powerrings around the fence and connect the pin vdd_core (only under module core1) to global net vdd_core1. the same for cores 2 to 5.
how can i restrict sroute to only route the standard cell vdd lanes inside the area of the module fences? outside the fences there will be no logic at all, only wires.
Ok, this should be pretty easy then. You might want to look at globalNetConnect -module to assign the different sources to the different core hierarchies.
For sroute, try putting placement blockages between the core fences. That should stop the followpin generation from happening between fences. If I've misunderstood, please post a picture - I'm sure we can get the tools to do what you want here.
sorry for the late reply. I was busy with paperwork. I managed to connect the global nets correctly and also constrainted the follow pins as you suggested. Now the next problem: When I add TieHiLow cells or do CTS, how can I control to which vcc_core_x (x in 1 to 5) the by Encounter added cells will be connected.
All cores are surrounded by a placement blockage as you suggested. All buffer/inverters added by CTS and the TieHighLow cells should be placed inside the corresponing fence andconnect the the vdd,vcc already routed there.
Thanks in advance