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Power domains or not?

schnufff

Hi all,

I have to setup a chip with 5 completely separated cores. Each core has its own vcc_core/io and vdd_core/io ind i/o pins.

But the actual voltage of all cores is 1.8V. For testing only one core should be active at a time.

Can I do this just with connectGlobalNet or is this more like a multi supply voltage flow with a single volate?

 

If there is some documentation about this topic, please give me a hint. The UserGuide didn't cover this topic.

Parents

  •  Hi Kari,

     

    sorry for the late reply. I was busy with paperwork. I managed to connect the global nets correctly and also constrainted the follow pins as you suggested. Now the next problem: When I add TieHiLow cells or do CTS, how can I control to which vcc_core_x (x in 1 to 5) the by Encounter added cells will be connected.

    All cores are surrounded by a placement blockage as you suggested. All buffer/inverters added by CTS and the TieHighLow cells should be placed inside the corresponing fence andconnect the the vdd,vcc already routed there.

    Thanks in advance

    Stefan

Reply

  •  Hi Kari,

     

    sorry for the late reply. I was busy with paperwork. I managed to connect the global nets correctly and also constrainted the follow pins as you suggested. Now the next problem: When I add TieHiLow cells or do CTS, how can I control to which vcc_core_x (x in 1 to 5) the by Encounter added cells will be connected.

    All cores are surrounded by a placement blockage as you suggested. All buffer/inverters added by CTS and the TieHighLow cells should be placed inside the corresponing fence andconnect the the vdd,vcc already routed there.

    Thanks in advance

    Stefan

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