I use clock gating in my design, but it seems the clock tree synthesis only balances the clock to the clock gating cell but not to the leaf register.
I have checked the post-layout simulation results. The clock signals to the gating cell are well aligned. But the gated clock signals to the leaf register are not well aligned.
Is there any solutions to let the tool balance the clock tree passing through the clock gating cell?
I have a doubt about the clock gating.
If the clock gating is used, the enable and data are actually bufferred by two different register. The enable is bufferred by the latch of the clock gating cell, and the data will be bufferred by the actual data register. But if the delay for the generated clock from gating cell to data register is large, the data maybe missed, since it should be sampled during the edge of clock, but now the clock is delayed for a certain time. Then how does it work? Is my understanding right?