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clock tree synthesis for clock gating

quiet

I use clock gating in my design, but it seems the clock tree synthesis only balances the clock to the clock gating cell but not to the leaf register.

I have checked the post-layout simulation results. The clock signals to the gating cell are well aligned. But the gated clock signals to the leaf register are not well aligned.

Is there any solutions to let the tool balance the clock tree passing through the clock gating cell?

Thanks.

  • Did you try the throughPin option in the clock specification file? Maybe it works.

    BR

    Yuqi 

  • Because I use design compile to add the clock gating cells automatically, it's hard to specify all the throughPins.
  • CTS should trace through the clock gates. What does your clock spec file look like? Do you have "noGating no"?

  • I just use the specification file that's generated by the tool automatically. Do i need to add more options?

    And the option nogating has been set to no.

  • Did buffering up to the leaf cells occur? If so, then the spec file is correct and working. Maybe it's just the skew results that you're not happy with? We'd need more information about the problem.

  • I have a doubt about the clock gating.

    If the clock gating is used, the enable and data are actually bufferred by two different register. The enable is bufferred by the latch of the clock gating cell, and the data will be bufferred by the actual data register. But if the delay for the generated clock from gating cell to data register is large, the data maybe missed, since it should be sampled during the edge of clock, but now the clock is delayed for a certain time. Then how does it work? Is my understanding right?

    Thanks.

  • Hi Kari,

    In my case too, buffering didnt occur after the ICG cell, the ICG cell directly drives around 500 flops spread across the design, resulting in huge skew and latency.

    I didset the NoGating to be NO, and I removed it too, but it both cases, it didnt make a difference.

    Any ideas, what might be wrong here.

    Thanks,
    Rajesh.'

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