I use clock gating in my design, but it seems the clock tree synthesis only balances the clock to the clock gating cell but not to the leaf register.
I have checked the post-layout simulation results. The clock signals to the gating cell are well aligned. But the gated clock signals to the leaf register are not well aligned.
Is there any solutions to let the tool balance the clock tree passing through the clock gating cell?
Did you try the throughPin option in the clock specification file? Maybe it works.
I just use the specification file that's generated by the tool automatically. Do i need to add more options?
And the option nogating has been set to no.