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clock tree synthesis for clock gating

quiet

I use clock gating in my design, but it seems the clock tree synthesis only balances the clock to the clock gating cell but not to the leaf register.

I have checked the post-layout simulation results. The clock signals to the gating cell are well aligned. But the gated clock signals to the leaf register are not well aligned.

Is there any solutions to let the tool balance the clock tree passing through the clock gating cell?

Thanks.

Parents
  • Hi Kari,

    In my case too, buffering didnt occur after the ICG cell, the ICG cell directly drives around 500 flops spread across the design, resulting in huge skew and latency.

    I didset the NoGating to be NO, and I removed it too, but it both cases, it didnt make a difference.

    Any ideas, what might be wrong here.

    Thanks,
    Rajesh.'
Reply
  • Hi Kari,

    In my case too, buffering didnt occur after the ICG cell, the ICG cell directly drives around 500 flops spread across the design, resulting in huge skew and latency.

    I didset the NoGating to be NO, and I removed it too, but it both cases, it didnt make a difference.

    Any ideas, what might be wrong here.

    Thanks,
    Rajesh.'
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