I have a block with the same structure (sub module) repeating many times. I have done manual placement & routing for one slice
and saved a design.
Now I need to instantiate and use a hand made slice many times (just like instantiating in layout editor)
Any ideas how I can do that?
Thanks in Advance,
Thank You. Yes, that's one of the ways. Actually I'm doing the design in block level, so I would skip splitting one
block to many LEFs. Is there any other way? I've read there's partitioning and master/clone technique, but I haven't figured
out how to do master/clone. I would appreciate if you can walk me through some steps
BTW, another issue here is that Encounter does not accept verilog netlists that have same cell instantiated more than once and asks to uniquify netlist with uniquifyNetlist utility. After that procedure extra modules are being generated (module_name_SPC1, module_name_SPC2, etc..) and unique cells are getting instantiated. Please let me know if explanation is not clear.
My point is in this case names for the same module become different, and how master/clone can be recognized?