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Nanoroute stops at Placement blockage

In my design with 5 cores I have a Placement blockage around each core. This was suggested by Kari to stop sroute from connecting all follow pins together. But now CTS and also nanoroute stops routing all signal that run from the cores trough the blockage to the IO pads.

I though its a placement blockage and not a routing blockage. Trial route works fine, but produces a lot of violations. What can I do to

allow nanoroute to pass trough the placement blockage?

Thanks

Stefan

Parents

schnufff over 12 years ago

Dear Kari,

I figured out, that is has nothing to do with the placement blockage.

Beside the "fully connected" attribute it seems to be related to these to errors:

#WARNING (NRDB-733) and #WARNING (NRDB-629)
A cadence solution points to a failure in the lef files:
http://support.cadence.com/wps/myportal/cos/COSHome/viewsolution/!ut/p/c5/dY1LkoIwAAXP4gGshDATkiXfBBCcKMhnQ6EOlApBgWLE04sHmH7LrlcNcrBMltOlLsdLJ8sGpCDHhYKYqfhfkG7NkECX4NDfHWy4AJLPAxfwH3QIMpBrH4-QQiBlTmRA1_Rdj2gqgj4GB9n17VKKQMpPvWF1QW3plojmhyOqweP345mcS8yGlm3qa9FTqXyf7IDQaaDzSzNUb_pbmwnEYkRzJA3ZPDkL91W841nftdaIvRw5P-JxLSr1yTekWrMmGUWc2_tOBE28pXpwa9NjtgIh79pfcL_Jl0P01RvvT9zz/dl3/d3/L2dBISEvZ0FBIS9nQSEh/

Because I get this for all signal to the IO cells.

I double checked not to route power signals and also looked into the used lef files

and they all look OK.

Pref tracks are covering the hole chip including the IO area.

And there are no special attributes on the signals,

they are all clock or just signal.

About the manual routing: I dont know how to do this and found no tutorial in the web. Sorry.

What else can be the problem?

Stefan
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schnufff over 12 years ago

Dear Kari,

I figured out, that is has nothing to do with the placement blockage.

Beside the "fully connected" attribute it seems to be related to these to errors:

#WARNING (NRDB-733) and #WARNING (NRDB-629)
A cadence solution points to a failure in the lef files:
http://support.cadence.com/wps/myportal/cos/COSHome/viewsolution/!ut/p/c5/dY1LkoIwAAXP4gGshDATkiXfBBCcKMhnQ6EOlApBgWLE04sHmH7LrlcNcrBMltOlLsdLJ8sGpCDHhYKYqfhfkG7NkECX4NDfHWy4AJLPAxfwH3QIMpBrH4-QQiBlTmRA1_Rdj2gqgj4GB9n17VKKQMpPvWF1QW3plojmhyOqweP345mcS8yGlm3qa9FTqXyf7IDQaaDzSzNUb_pbmwnEYkRzJA3ZPDkL91W841nftdaIvRw5P-JxLSr1yTekWrMmGUWc2_tOBE28pXpwa9NjtgIh79pfcL_Jl0P01RvvT9zz/dl3/d3/L2dBISEvZ0FBIS9nQSEh/

Because I get this for all signal to the IO cells.

I double checked not to route power signals and also looked into the used lef files

and they all look OK.

Pref tracks are covering the hole chip including the IO area.

And there are no special attributes on the signals,

they are all clock or just signal.

About the manual routing: I dont know how to do this and found no tutorial in the web. Sorry.

What else can be the problem?

Stefan
Cancel
Vote Up 0 Vote Down

Cancel

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