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Nanoroute stops at Placement blockage

In my design with 5 cores I have a Placement blockage around each core. This was suggested by Kari to stop sroute from connecting all follow pins together. But now CTS and also nanoroute stops routing all signal that run from the cores trough the blockage to the IO pads.

I though its a placement blockage and not a routing blockage. Trial route works fine, but produces a lot of violations. What can I do to

allow nanoroute to pass trough the placement blockage?

Thanks

Stefan

schnufff over 12 years ago

I think it has to do with the following error:
NET $net is marked as fully connected but pin $pin of instance $instance is not yet connected.
This is repeated for all toplevel nets going to the IO cells. How can I reset these nets, so that they will be routed again?

Stefan
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Kari over 12 years ago

The placement blockage won't block routing. Something else is going on here. Can you turn on the routing grids to make sure they cover the area between the core and I/O? (they're called Pref Track, you can check layer by layer). If those look good, can you complete one of these routes by hand? Trying that may show error markers or something that leads you to the cause. Are the nets in question marked SPECIAL, or do they have a skip_routing attribute on them?
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schnufff over 12 years ago

Dear Kari,

I figured out, that is has nothing to do with the placement blockage.

Beside the "fully connected" attribute it seems to be related to these to errors:

#WARNING (NRDB-733) and #WARNING (NRDB-629)
A cadence solution points to a failure in the lef files:
http://support.cadence.com/wps/myportal/cos/COSHome/viewsolution/!ut/p/c5/dY1LkoIwAAXP4gGshDATkiXfBBCcKMhnQ6EOlApBgWLE04sHmH7LrlcNcrBMltOlLsdLJ8sGpCDHhYKYqfhfkG7NkECX4NDfHWy4AJLPAxfwH3QIMpBrH4-QQiBlTmRA1_Rdj2gqgj4GB9n17VKKQMpPvWF1QW3plojmhyOqweP345mcS8yGlm3qa9FTqXyf7IDQaaDzSzNUb_pbmwnEYkRzJA3ZPDkL91W841nftdaIvRw5P-JxLSr1yTekWrMmGUWc2_tOBE28pXpwa9NjtgIh79pfcL_Jl0P01RvvT9zz/dl3/d3/L2dBISEvZ0FBIS9nQSEh/

Because I get this for all signal to the IO cells.

I double checked not to route power signals and also looked into the used lef files

and they all look OK.

Pref tracks are covering the hole chip including the IO area.

And there are no special attributes on the signals,

they are all clock or just signal.

About the manual routing: I dont know how to do this and found no tutorial in the web. Sorry.

What else can be the problem?

Stefan
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Kari over 12 years ago

It sounds like your IO LEFs don't have physical pins defined. If you zoom in to the I/O cell, do you see pin shapes? You already said you checked the LEF...
To try routing a net by hand, see the "Editing Wires" chapter in the User Guide.
Are those nets considered "SPECIAL" nets? (If you output a DEF, do you find these nets in the NETS section, or the SPECIALNETS section?)
Try these things and see what happens next - hard to debug from a distance, but hopefully we can get to the bottom of it.
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Kari over 12 years ago

also, check out this blog entry for wire editing:
/blogs/di/archive/2010/01/21/encounter-screencast-editing-wires-more-quickly-with-bindkeys.aspx
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schnufff over 12 years ago

Hi Kari,
after reading the manual, I am able to route the wires manually without problems. I also can see the pins of the IOs at layer M2 and M3.
There is no attribute like special/power/whatever set to the wires. The lef files of the cells have CLASS PAD INOUT, the Pins have USE SIGNAL, and a PORT definition with the metal layers. In the def file, in SPECIALNETS are only the power nets and in NETS are all the signal as expected.I am unshure if tis an error within the lef files are some tool set these "fully connected" attribute wrong. Trial route is connecting the IO-wires correct! So the physical pins seem to be there.

Thanks
Stefan
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Kari over 12 years ago

Well, at least now we know the net CAN be connected, so that's good. Try using nanoroute for selected nets only, and just select ONE of these nets. Maybe the messasges will give more info about why it can't route.
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