In my design with 5 cores I have a Placement blockage around each core. This was suggested by Kari to stop sroute from connecting all follow pins together. But now CTS and also nanoroute stops routing all signal that run from the cores trough the blockage to the IO pads.
I though its a placement blockage and not a routing blockage. Trial route works fine, but produces a lot of violations. What can I do to
allow nanoroute to pass trough the placement blockage?
after reading the manual, I am able to route the wires manually without problems. I also can see the pins of the IOs at layer M2 and M3.
There is no attribute like special/power/whatever set to the wires. The lef files of the cells have CLASS PAD INOUT, the Pins have USE SIGNAL, and a PORT definition with the metal layers. In the def file, in SPECIALNETS are only the power nets and in NETS are all the signal as expected.I am unshure if tis an error within the lef files are some tool set these "fully connected" attribute wrong. Trial route is connecting the IO-wires correct! So the physical pins seem to be there.