Stats

  • Locked Locked
  • Replies 4
  • Subscribers 92
  • Views 4863
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Clock Tree Synthesis - Not able to add clock buffers

Northfork

Hi all,

 I'm running a script that was given to me for clock tree synthesis, but no buffers are being inserted in my clock tree. I only have 240 sinks (flip-flops) and one clock input pin in my design. I suspect the problem is due to my power domain specification, but I cannot figure it out. The basic scheme I am trying to recreate:
The design is primarily an input to reg path, in which I have specified each cell one logic depth before a flip flop to be in a different power domain (via CPF). The reason I created this power domain is that I want those cells to be connected to a virtual rail that I can monitor with a separate analog macro. However, both power domains will be running at the same nominal voltage (0.6 V, and the domain with the virtual rail may see a little drop-but that is not the main concern).

When I try to run: ckSynthesis -rguide ${top_level}.cts.rguide -report ${top_level}.ctsrpt -macromodel ${top_level}.ctsmdl -forceReconvergent

No clock tree buffers are added. I have attached the log file and cts file I am using. I know there is enough space in my design for buffers to be added.

Newbie student here, so ANY advice or help is appreciated. (i'm using 130 nm ibm13, 1.2V but my design is low power/using a library characterized at 0.6 V). Thanks for your time!

  • I have reattached a new cts report. I cannot understand why the actual Max. Rise Sink tran and Max. Fall Sink Tran are so big (would this problem arise from incorrect library characterization?). Please see the attached file for more details.

    Actual Max. Rise Sink Tran            : 391862(ps)                   

    Actual Max. Fall Sink Tran            : 12150.8(ps)            

    Anyways, the tool will still not generate/buffer the clock tree. I also get the following message :

    SubTree No: 0

    Input_Pin:  (NULL)

    Output_Pin:  (clock)

    Output_Net: (clock) DontTouch (Special PowerDomain Case)

     Is clock tree synthesis different for MSV designs? (Either way, both my power domains are at the same voltage, I only use an additional domain to allow me to connect cells in that domain to a rail that i want to monitor, (current sensing completion detection))

    In the end the clock tree is just a bunch of long wires connected to the 240 flip flops. 

    Any help or advice is extremely appreciated.

    Thanks!                                      

  • did you have a CTS spec file for this clock? (.ctstch file)
  • Hi, I had the same Issue. Did you solve it? How? Thanks, Salva

  • I have not dealt with multi voltage / CPF layouts yet, so I can't help you there.
    The only thing I can think of is that your clock pin boundary conditions may be so wildly off target that CTS feels that no buffers are required. Almost as if the clk_in pin has infinite drive.

    There are a couple of .ctstch commands that may be useful bolded below ... this is my current CTS start point.


    Shawn

     

    ###############################################################
    #  Generated by:      Cadence Encounter 10.12-s181_1
    #  OS:                Linux x86_64(Host ID pcary670.ott.ciena.com)
    #  Generated on:      Thu Jan  5 10:27:12 2012
    #  Design:            frnt_datapath_wrap
    #  Command:           clockDesign -genSpecOnly frnt_datapath_wrap.ctstch
    ###############################################################
    #-- Special Route Type --
    RouteTypeName CTSRoute22
    NONDEFAULTRULE DBLCUT_DBLSPACE_RULE
    TopPreferredLayer 7
    BottomPreferredLayer 6
    PreferredExtraSpace 0
    End

    #-- Special Route Type --
    RouteTypeName CTSRoute
    NONDEFAULTRULE DBLCUT_RULE
    TopPreferredLayer 8
    BottomPreferredLayer 7
    PreferredExtraSpace 2
    End


    #-- Regular Route Type --
    RouteTypeName CTSLeafRoute
    NONDEFAULTRULE DBLCUT_RULE
    TopPreferredLayer 6
    BottomPreferredLayer 3
    PreferredExtraSpace 1
    End

    #-- Clock Group --
    #ClkGroup
    #+ <clockName>


    #------------------------------------------------------------
    # Clock Root   : i_LINE_CLK
    # Clock Name   : LINE_CLK
    # Clock Period : 3.236ns
    #------------------------------------------------------------
    AutoCTSRootPin i_LINE_CLK
    Period         3.236ns
    MaxDelay       0.01ns # sdc driven default
    MinDelay       0ns # sdc driven default
    MaxSkew        220ps # sdc driven default
    SinkMaxTran    125ps # sdc driven default
    BufMaxTran     110ps # sdc driven default
    Buffer         HS65_LL_CNBFX62 HS65_LL_CNBFX27
    ForceMaxTran YES
    NoGating       NO
    DetailReport   YES
    #SetDPinAsSync  NO
    #SetIoPinAsSync NO
    #SetASyncSRPinAsSync  NO
    #SetTriStEnPinAsSync NO
    #SetBBoxPinAsSync NO
    RouteClkNet    YES
    PostOpt        YES
    OptAddBuffer   YES
    RouteType      CTSRoute22
    LeafRouteType  CTSLeafRoute
    AddDriverCell  HS65_LL_CNBFX62
    LeafBuffer     HS65_LL_CNBFX27
    Obstruction    YES
    CellObstruction
    + ST_DPHD_256x36m4_b Entire
    + ST_DPREG_288x128m2 Entire
    MaxFanout      32
    ForceMaxFanout YES
    CellHalo
    + HS65_LL_CNBFX62 17.2 2.6
    + HS65_LL_CNBFX27 18.8 2.6
    + HS65_LLP_CNHLSX62 17.2 2.6
    MaxCap
    + HS65_LL_CNBFX62 150fF
    + HS65_LL_CNBFX27 150fF
    MaxDistance 825
    END

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.