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Clock Tree Synthesis - Not able to add clock buffers

Northfork

Hi all,

 I'm running a script that was given to me for clock tree synthesis, but no buffers are being inserted in my clock tree. I only have 240 sinks (flip-flops) and one clock input pin in my design. I suspect the problem is due to my power domain specification, but I cannot figure it out. The basic scheme I am trying to recreate:
The design is primarily an input to reg path, in which I have specified each cell one logic depth before a flip flop to be in a different power domain (via CPF). The reason I created this power domain is that I want those cells to be connected to a virtual rail that I can monitor with a separate analog macro. However, both power domains will be running at the same nominal voltage (0.6 V, and the domain with the virtual rail may see a little drop-but that is not the main concern).

When I try to run: ckSynthesis -rguide ${top_level}.cts.rguide -report ${top_level}.ctsrpt -macromodel ${top_level}.ctsmdl -forceReconvergent

No clock tree buffers are added. I have attached the log file and cts file I am using. I know there is enough space in my design for buffers to be added.

Newbie student here, so ANY advice or help is appreciated. (i'm using 130 nm ibm13, 1.2V but my design is low power/using a library characterized at 0.6 V). Thanks for your time!

Parents

  • I have reattached a new cts report. I cannot understand why the actual Max. Rise Sink tran and Max. Fall Sink Tran are so big (would this problem arise from incorrect library characterization?). Please see the attached file for more details.

    Actual Max. Rise Sink Tran            : 391862(ps)                   

    Actual Max. Fall Sink Tran            : 12150.8(ps)            

    Anyways, the tool will still not generate/buffer the clock tree. I also get the following message :

    SubTree No: 0

    Input_Pin:  (NULL)

    Output_Pin:  (clock)

    Output_Net: (clock) DontTouch (Special PowerDomain Case)

     Is clock tree synthesis different for MSV designs? (Either way, both my power domains are at the same voltage, I only use an additional domain to allow me to connect cells in that domain to a rail that i want to monitor, (current sensing completion detection))

    In the end the clock tree is just a bunch of long wires connected to the 240 flip flops. 

    Any help or advice is extremely appreciated.

    Thanks!                                      

Reply

  • I have reattached a new cts report. I cannot understand why the actual Max. Rise Sink tran and Max. Fall Sink Tran are so big (would this problem arise from incorrect library characterization?). Please see the attached file for more details.

    Actual Max. Rise Sink Tran            : 391862(ps)                   

    Actual Max. Fall Sink Tran            : 12150.8(ps)            

    Anyways, the tool will still not generate/buffer the clock tree. I also get the following message :

    SubTree No: 0

    Input_Pin:  (NULL)

    Output_Pin:  (clock)

    Output_Net: (clock) DontTouch (Special PowerDomain Case)

     Is clock tree synthesis different for MSV designs? (Either way, both my power domains are at the same voltage, I only use an additional domain to allow me to connect cells in that domain to a rail that i want to monitor, (current sensing completion detection))

    In the end the clock tree is just a bunch of long wires connected to the 240 flip flops. 

    Any help or advice is extremely appreciated.

    Thanks!                                      

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