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encounter streamout by preserving the partition

Shiny
After floorplanning my design in Encounter, I specified partition to few of my blocks in the design. I did gds streamout and imported the .gds file to virtuoso. The netlist extracted from virtuoso do not show the partitions. How should I preserve the partioning all the way until the netlist phase? Please help me out!

  • The GDS format essentially defines the physical metal geometries and text in the design. It is not for translating floorplan constraints such as partitions. Can you explain what you are trying to do?

    The Mixed Signal Interoperability Guide (http://support.cadence.com/wps/mypoc/cos?uri=deeplinkmin:DocumentViewer;src=pubs;q=dmsflow/dmsflow13.1/dmsflowTOC.html) explains the mixed signal flows and how to pass partition information to Virtuoso for implementing analog blocks.

    Brian

  • Hi Brian,

    Thanks for responding! I started with a vhdl behavioral filter design, did structural synthesis using Cadence BuildGates, place and route with soc encounter, imported output of encounter to virtuoso and extracted spice netlist using divaEXT.rul. My experimentation is supposed to be on the spice netlist.

    The problem is I need to insert sensors in the filter design and connect them to certain modules. I have a transistor level implementation of filter (it cannot be represented as a gate level design). I was confused where to insert it in the flow so I specified those certain modules as partitions in soc encounter expecting a final structural netlist where I thought I could insert the sensors. But it is not working.

    Can you suggest me another way to insert my filters in the flow?

    Thanks a lot,

    Shiny 

     

  • Hello Shiny,

    If you have a LEF representation of the sensors you can instantiate them in the Verilog netlist and place&route them in Encounter. The output Verilog netlist and GDS would have an instantiation of the sensors.

    I also recommend posting your question to the Custom IC Design forum to see if you can accomplish what you want in Virtuoso.

    Brian

  • Thanks Brian! I will look into that.
  • Hi Brian,

    I tried converting my transistor level hspice netlist of sensor into lef format, instantiated in verilog  and did place-and-route in encounter. But in place phase, the standard cells are populated in the entire circuit except  in the sensors since the are not described as netlist with standard cells to start with. In the final gds, the sensor location came out as empty. Please let me know if my flow has a problem.
    Also, I was not able to access the mixed signal interoperability guide that you suggested me to. If possible, could you send me the file to spendya2@mail.usf.edu so I will try to find solution to my problem from the interoperability guide?

    Thanks a lot,
    Shiny

  • The DMS Flow doc is also available in your installation. It can be access using 'cdnshelp' or under the Help menu. The PDF is at:

    <install_dir>/doc/dmsflow/dmsflow.pdf

    Did you define the physical geometry of the sensor circuit in its LEF definition? It will likely be CLASS BLOCK and the SIZE statement will define its physical size. Then you can define PINS as needed. If the sensor circuit is physically defined then placeDesign should place it.

    Brian

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