The GDS format essentially defines the physical metal geometries and text in the design. It is not for translating floorplan constraints such as partitions. Can you explain what you are trying to do?
The Mixed Signal Interoperability Guide (http://support.cadence.com/wps/mypoc/cos?uri=deeplinkmin:DocumentViewer;src=pubs;q=dmsflow/dmsflow13.1/dmsflowTOC.html) explains the mixed signal flows and how to pass partition information to Virtuoso for implementing analog blocks.
Thanks for responding! I started with a vhdl behavioral filter design, did structural synthesis using Cadence BuildGates, place and route with soc encounter, imported output of encounter to virtuoso and extracted spice netlist using divaEXT.rul. My experimentation is supposed to be on the spice netlist.
The problem is I need to insert sensors in the filter design and connect them to certain modules. I have a transistor level implementation of filter (it cannot be represented as a gate level design). I was confused where to insert it in the flow so I specified those certain modules as partitions in soc encounter expecting a final structural netlist where I thought I could insert the sensors. But it is not working.
Can you suggest me another way to insert my filters in the flow?
Thanks a lot,
If you have a LEF representation of the sensors you can instantiate them in the Verilog netlist and place&route them in Encounter. The output Verilog netlist and GDS would have an instantiation of the sensors.
I also recommend posting your question to the Custom IC Design forum to see if you can accomplish what you want in Virtuoso.