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Encounter final layout export to Cadence Virtuoso

Kabal

Hello,

I am now starting to read and going through the process of digital flow.

What is the best way to export the final routed and placed design in encounter to Cadence Virtuoso environment for the subsequent DRC and LVS?

As far as I saw already from several manuals, one way is to save the GDS, then go through the process of importing GDS inside Virtuoso in a new library, a process with which I am familiar with. Then of course one can perform DRC there with Assura. And then if I am correct, that library can be used in any of a custom designed analog block in another library within Virtuoso environment.

But question is, what if the digital design was fully done using the HDL (vhdl or verilog), how does one perform LVS then once the GDS was imported in the Cadence Virtuoso environment?

When I design analog circuits, LVS compares my custom layout against the CDL-type netlist which is generated from the schematics I manually build.

But if I imported the GDS layout of automatically placed and routed digital design by encounter, how do I set up the process for LVS to compare it with HDL description? Or in what other proper way this has to be done?

 

  • Hi Kabal, You can import your Verilog netlist (the one after synthesis, that you used to start the P&R) into Virtuoso with File->Impot->Verilog from the CIW.
  • you output a physical verilog (saveNetlist -phys) then convert that to CDL. That method will depend on which LVS tool you are using.

  • What is the best way to convert the result of saveNetlist -phys to CDL? 

    Because the way I did it:

    1) Import physical verilog to CIW  as schematics

    2) There from schematics create CDL netlist, then CDL netlist for LVS using preprocessor supplied by kit (the way I always produce netlist for LVS on all my hand made analog circuits, and that way works of course)

    But there is a problem, first of all, even though schematics is created and looks big and have all those standard cells, when I tried to look inside those standard cells out of which my big schematics imported from physical Verilog composed I noticed there are NO TRANSISTORS, just ports... is this normal? This looks suspicious to me.

    Anyway, I still tried from now on to do the LVS as I always do on all my cusotm circuits, but the LVS spits out errors something like:  nfet(MOS) on Layout is unbound to any Schematic device.. 

    So, the bottom line is, after Encounter import, the layout was corrected for residual DRC errors and was looking sexy, the physical Verilog produced by Encounter was imported, schematics of my big digital unit created on a gate level, but each gate had empty schematic inside, and LVS gave that error above.

    Why would that happen? And the big question is, how do I import the physical verilog so that the CDL schematics with transistors is created, so that I can do the LVS, because the layout from transistors of course requires schematics with transistors at the bottom level for successfull LVS.

    Any ideas? 

  • if you're using PVS, you can use the v2cdl command. If you're using Calbire, you use the v2lvs command. In either one you would point to the spice files of your std cells, macros, etc.

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