Encounter final layout export to Cadence Virtuoso

Hello,

I am now starting to read and going through the process of digital flow.

What is the best way to export the final routed and placed design in encounter to Cadence Virtuoso environment for the subsequent DRC and LVS?

As far as I saw already from several manuals, one way is to save the GDS, then go through the process of importing GDS inside Virtuoso in a new library, a process with which I am familiar with. Then of course one can perform DRC there with Assura. And then if I am correct, that library can be used in any of a custom designed analog block in another library within Virtuoso environment.

But question is, what if the digital design was fully done using the HDL (vhdl or verilog), how does one perform LVS then once the GDS was imported in the Cadence Virtuoso environment?

When I design analog circuits, LVS compares my custom layout against the CDL-type netlist which is generated from the schematics I manually build.

But if I imported the GDS layout of automatically placed and routed digital design by encounter, how do I set up the process for LVS to compare it with HDL description? Or in what other proper way this has to be done?