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Clock Tree Synthesis Through Narrow Corridors

dfick

 Hi,

 I'm running clock tree synthesis on a large memory-like array structure where there are narrow corridors between some of the rows/columns. EDI CTS is having a hard time and is creating many buffers in the middle of the design, with huge congestion. Is there anything in particular that I should be looking at for this scenario?

 Thanks

Parents

  • Obstruction's are another  <DESIGN>.ctstch  option worth trying..............

    AutoCTSRootPin ................
    Obstruction    YES
    CellObstruction
    + ST_SPHS_SLRH_16384x39m16B4_bTR0P Entire
    + ST_SPREG_LRH_4096x36m8B2_bTR Entire
    + ST_DPHS_SLRH_4096x32m8B2_T0P Entire
    + ST_ROM_R_16384x32m32B4_Tol Entire
    + ARM_hard_core Entire
    END


     Shawn

Reply

  • Obstruction's are another  <DESIGN>.ctstch  option worth trying..............

    AutoCTSRootPin ................
    Obstruction    YES
    CellObstruction
    + ST_SPHS_SLRH_16384x39m16B4_bTR0P Entire
    + ST_SPREG_LRH_4096x36m8B2_bTR Entire
    + ST_DPHS_SLRH_4096x32m8B2_T0P Entire
    + ST_ROM_R_16384x32m32B4_Tol Entire
    + ARM_hard_core Entire
    END


     Shawn

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