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Short violation

skow
skow over 11 years ago

 I did a verifyGeometry right after placeDesign -prePlaceOpt and had 1000 short violations.

The messages are : SHORT:

Special Wire of Net VSS & Pin of Cell U7178  ( M1 )
Bounds : ( 277.600, 31.035 ) ( 280.600, 31.365 )

SHORT: Special Via of Net VDD & Pin of Cell U35043  ( M1 )
Bounds : ( 348.000, 14.835 ) ( 351.000, 15.165 )

The display showed the short aligned with the power stripes; I did the previous short violation's suggestion to ensure VDD, VSS are properly set. The standard cell is provided by foundry so it should be fine. Is there anything else I missed?

 

 

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  • skow
    skow over 11 years ago

     I have

    set rda_Input(ui_pwrnet) {vdd}
    set rda_Input(ui_gndnet) {vss}
    set rda_Input(PIN:VDD:) {vdd}
    set rda_Input(PIN:VSS:) {vss}
    set rda_Input(TIEHI::) {vdd}
    set rda_Input(TIELO::) {vss}
    and it failed the same so I use

    globalNetConnect VSS -type pgpin -pin VSS -all -override
    globalNetConnect VDD -type pgpin -pin VDD -all -override cmd again before the placement then verify geometry. The short violations are gone. Why the .conf did not work?

     

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  • skow
    skow over 11 years ago

     I have

    set rda_Input(ui_pwrnet) {vdd}
    set rda_Input(ui_gndnet) {vss}
    set rda_Input(PIN:VDD:) {vdd}
    set rda_Input(PIN:VSS:) {vss}
    set rda_Input(TIEHI::) {vdd}
    set rda_Input(TIELO::) {vss}
    and it failed the same so I use

    globalNetConnect VSS -type pgpin -pin VSS -all -override
    globalNetConnect VDD -type pgpin -pin VDD -all -override cmd again before the placement then verify geometry. The short violations are gone. Why the .conf did not work?

     

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