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LVS Fails, after P&R extra pins in layout

Hello all

When runing LVS with Calibre, it fails because the layout has more pins than the schematic. Digging into it, it turned out that when streaming in the gds file generated by encounter I got labels in the internal nets. If I remove those labels, then the issue is solved.

I wonder what should I setup to avoid those labels in the internal nets? I have been stearing at the streamout.map file, the cds2gds.map and the technology file, but can't find anything that ring any bell.

Finally, we used to work with IC51 and now we are working in IC61. Does that make any difference?

Thanks!

Patricia

Parents

PatriciaG over 10 years ago

This is the stream map file

...
M1 NET 15 0
M1 SPNET 15 0
M1 VIA 15 0
M1 PIN 15 0
M1 LEFPIN 15 0
M1 FILL 15 0
M1 FILLOPC 15 0
M1 LEFOBS 15 0
M1 VIAFILL 15 0
M1 VIAFILLOPC 15 0
NAME M1/NET 15 20
NAME M1/SPNET 15 20
NAME M1/PIN 15 20
NAME M1/LEFPIN 15 20
...
COMP ALL 212 0
DIEAREA ALL 212 0
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PatriciaG over 10 years ago

This is the stream map file

...
M1 NET 15 0
M1 SPNET 15 0
M1 VIA 15 0
M1 PIN 15 0
M1 LEFPIN 15 0
M1 FILL 15 0
M1 FILLOPC 15 0
M1 LEFOBS 15 0
M1 VIAFILL 15 0
M1 VIAFILLOPC 15 0
NAME M1/NET 15 20
NAME M1/SPNET 15 20
NAME M1/PIN 15 20
NAME M1/LEFPIN 15 20
...
COMP ALL 212 0
DIEAREA ALL 212 0
Cancel
Vote Up 0 Vote Down

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