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LVS Fails, after P&R extra pins in layout

PatriciaG

Hello all
 
When runing LVS with Calibre, it fails because the layout has more pins than the schematic. Digging into it, it turned out that when streaming in the gds file generated by encounter I got labels in the internal nets. If I remove those labels, then the issue is solved.
 
I wonder what should I setup to avoid those labels in the internal nets? I have been stearing at the streamout.map file, the cds2gds.map and the technology file, but can't find anything that ring any bell.
Finally, we used to work with IC51 and now we are working in IC61. Does that make any difference? 
 
Thanks!
Patricia 
 
 
Parents
  • The only NAME lines I typically use are the PIN ones. Comment out the other NAME lines (NET, SPNET, LEFPIN, etc.) and see if that helps. If it does, you can add them back one at a time (if needed at all) and figure out which one is causing trouble.
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  • The only NAME lines I typically use are the PIN ones. Comment out the other NAME lines (NET, SPNET, LEFPIN, etc.) and see if that helps. If it does, you can add them back one at a time (if needed at all) and figure out which one is causing trouble.
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