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Design is tight after placing cells

PatriciaG

Hello 

After placing a design all the cells are concentrated in one place, the tool takes a very long time to finish and after a lot of iterations I have geometry and shorts violations.

I set the Clock to a very low frequency (in ps) hoping to relax the timing constrains in rtl compiler. 

Period      5000000  

Delay       10000    

OutDelay 10000   

 I also used :

 modulePadding -uniformDensity true 

The utilization is very low as well (0.4)   

Also, during routing I got the following warnings from encounter:

#WARNING (NREX-28) The height of the first routing layer M1 is 0.000000. It should be larger than 0.000000

#WARNING (NREX-29) The metal thickness of routing layer M1 is 0.000000. It should be larger than 0.0. Add this to the technology information for better accuracy.

#WARNING (NREX-30) Please also check the height and metal thickness values for the routing layers heigher than routing layer M1

#WARNING (NREX-4) No Extended Cap Table was imported. Not enough process information was provided either and default Extended Cap Table database will be used.

#WARNING (NRAG-41) The M1 user tracks are removed and regenerated from M3

# M1           H   Track-Pitch = 0.200    Line-2-Via Pitch = 0.205

#WARNING (NRAG-44) Track pitch is too small compared with line-2-via pitch 

 So I have two questions,

- How can I make sure the cells are spread a better in all the available area? 

- For the warnings: To fix it, should i set a parameter in the lef file? if so, which one?

Thanks! 

  • sounds like you're not reading in a captable or qrcTechFile
  • Thanks Kari. A related question, In the technology manual they give me the Layout grid and the vertical/horizontal pin grid. How do I translate this numbers to my LEF file?
  • If by "layout grid", you mean the manufacturing grid, that should already be in your tech LEF. I'm not sure what you mean by the vertical/horizontal pin grid.
  • Hello Kari, I guess I am not sure either. I have the manufacturing grid in the LEF which is 0.001, but in the standard cells manual they mention these other parameters. Layout grid, and vertical and horizontal pin grid. The problem is that I have around 1000 violations between spacing and shorts and i am trying to figure out how to modify the LEF to fix those. My guess is that I need to modify the OFFSET parameter for the routing layers but I am not sure how to calculate that OFFSET, or if I am following the right approach.
  • that's the right LEF param for manufacturing grid, so you're good there. maybe the other stuff is the routing tracks, that's what it sounds like. sometimes they are offset by 1/2 track so that they line up with the std cell pins. when you turn on the routing tracks, do the std cell pins fall on track intersections? if not, you may need to adjust the OFFSET or the tracks themselves, but EDI usually puts them in the right place. check that and post a few pictures if you can, if you need more help.

  • Hello Kari

    Can I turn on the routing tracks in encounter or should I import the design in virtuoso? Also, When I run a verify geometry (with the option Off Routing Grid checked) and checkTracks it seems that the majority of the pins are out of track. The figure below is a sample of a standard cell with off routing grid pins that I get.

  • you can absolutely turn on the routing tracks in encounter!

  • I am using encounter version 10.10. I guess the one in the figure is a newer version? do you know how to turn it on in this older version of encounter?
  • Click on the "all colors' button, then choose the view-only tab. you should see "pref track" there. then you can control which layer tracks by the usual way. at least I think that's how it would be, 10.x is kind of old :-)

  • That worked for the routing tracks, which was very helpful. All the pins seem on grid and even the metal routing look ok. The problem seem to be related with the way it places the VIAS. The majority of the errors involve a VIA to VIA or VIA to wire short or spacing violation like in the figure below. Do you know how can I fix those?

      

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