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CPF style with analog hard macro

GabrielB

Dear all,

hopefully I'm not writing in the wrong forum - but I saw most CPF related posts are here.

I'm designing a mixed signal ASIC with digital-on-top methodology. I have only one big analog custom hard block, for which I generated the abstract view and wrote by hand a liberty file. My problems arise, since this block needs 6 power supply voltages and 4 grounds. All this voltages together with all analog signals are directly connected to pads. All the digital ports of the block belongs to a single 3.3V power domain.


I'm writing in CPF 2.0 so I can use the set_analog_ports command and the set_macro_model with set_instance -model.

Now: should I define 6 different power domains for my macro and therefore also in my top design?

I tried defining only one 3.3V power domain, but then what about all the power and ground ports?


Thanks in advance

Gabriel

PS: I'm working with conformal 14.10.220, RC 14.11.000 and EDI 14.13

Parents
  • Gabriel:
    I would concentrate on writing your analog wrapper and power pad connections EXACTLY the way you intend to implement your design.
    Analog analog_inst \
    (.avdd_apin (avdd_anet), . avdd_bpin (avdd_bnet), . avdd_cpin (avdd_cnet] \
    (.agnd_apin (agnd_anet), . agnd_bpin (agnd_bnet) \
    );
    Bump avdd_abump (.bump_pin (avdd_anet));

    The digital vdd and gnd are typically implied in a gate level netlist and are connected by EDI applyGlobalNets.
    The digital side is where the power of CPF comes into play , it allows you to deviate from a homogenous digital power plane.
    Low power techniques like voltage islands etc. were a complete bear to layout and verify before CPF automated this process.
    Shawn
Reply
  • Gabriel:
    I would concentrate on writing your analog wrapper and power pad connections EXACTLY the way you intend to implement your design.
    Analog analog_inst \
    (.avdd_apin (avdd_anet), . avdd_bpin (avdd_bnet), . avdd_cpin (avdd_cnet] \
    (.agnd_apin (agnd_anet), . agnd_bpin (agnd_bnet) \
    );
    Bump avdd_abump (.bump_pin (avdd_anet));

    The digital vdd and gnd are typically implied in a gate level netlist and are connected by EDI applyGlobalNets.
    The digital side is where the power of CPF comes into play , it allows you to deviate from a homogenous digital power plane.
    Low power techniques like voltage islands etc. were a complete bear to layout and verify before CPF automated this process.
    Shawn
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