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How to write sdc for pre/post CTS ?

yamakazu

I want to set different clock uncertainity values in the same sdc file for both pre and post CTS modes. Can I do that ? The following sdc didn't work. How to do that ?

if {[getAnalysisMode -clockPropagation -quiet] == "forcedIdeal"} {
    set jit_add 0.2
} else {
    set jit_add 0
}
set_clock_uncertainty [expr 0.200+${jit_add}] \
  -from [get_clocks {my_clk}] -to [get_clocks {my_clk}]

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  • fitz
    One ideal constraint file for each mode, typically 2 functional and 3 DFT modes.
    clockDesign -update_io_latency will automatically propagate the real clocks and adjust the virtual clock latencies to match.
    So technically you do have separate preCTS and postCTS constraints for each mode, but the postCTS file are generated for you.

    Shawn
Reply
  • fitz
    One ideal constraint file for each mode, typically 2 functional and 3 DFT modes.
    clockDesign -update_io_latency will automatically propagate the real clocks and adjust the virtual clock latencies to match.
    So technically you do have separate preCTS and postCTS constraints for each mode, but the postCTS file are generated for you.

    Shawn
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