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RTL compiler technology transformation

kenambo

Hi all,  

I am converting an already synthesized netlist to another technology using RTL compiler.. while doing this the generic netlist coud not generate a scan latch. It just reflects the same name in the generic netlist.

For scan flops we can unmap scan flops using,     set_attribute unmap_scan_flops true  . but for latches it doesn't apply...

so please share anything that makes this possilble.

Tanks

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  • Hi kenambo,

    Hard to answer without more information.

    I think what you need to understand is how the'latches' got in there in the first place. unmap_scan_flops should handle any cells with a scan equivalent irrespective of LSSD, FF, master-slave, etc.

    If the cell was hand instantiated, it is possible the tool does not know how or simply is not possible to represent in RTL. For example, a memory cannot be unmapped since most tools cannot infer a memory from ANY RTL.

    I am also puzzed since you indicate your design has scan latches and scan flops. This seems strange since normally you would follow a single scan methodology. Lastly, not sure what you mean by scan latches. Are these LSSD latches, master/slave latches. Latches normally do not get scan replaced hence the confusion.

    You can provide the library description of the latch and its scan equivalent and we can see if, at least, the library, has all correct construct for the tool to go from test_cell to non test and viceversa

    regards,

    gh-

Reply

  • Hi kenambo,

    Hard to answer without more information.

    I think what you need to understand is how the'latches' got in there in the first place. unmap_scan_flops should handle any cells with a scan equivalent irrespective of LSSD, FF, master-slave, etc.

    If the cell was hand instantiated, it is possible the tool does not know how or simply is not possible to represent in RTL. For example, a memory cannot be unmapped since most tools cannot infer a memory from ANY RTL.

    I am also puzzed since you indicate your design has scan latches and scan flops. This seems strange since normally you would follow a single scan methodology. Lastly, not sure what you mean by scan latches. Are these LSSD latches, master/slave latches. Latches normally do not get scan replaced hence the confusion.

    You can provide the library description of the latch and its scan equivalent and we can see if, at least, the library, has all correct construct for the tool to go from test_cell to non test and viceversa

    regards,

    gh-

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