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RTL compiler technology transformation

kenambo

Hi all,  

I am converting an already synthesized netlist to another technology using RTL compiler.. while doing this the generic netlist coud not generate a scan latch. It just reflects the same name in the generic netlist.

For scan flops we can unmap scan flops using,     set_attribute unmap_scan_flops true  . but for latches it doesn't apply...

so please share anything that makes this possilble.

Tanks

Parents
  • CGICs cannot be inferred from HDL hence cannot be 'uninferred'. You can indeed do 'clock_gating remove' and then rely on them being added again but I believe change_link is a better approach. Note change_link can relink to a module/subdesign so if your library does not have one, you would have to create a module/subdesign for it using latches/or/etc.

    gh-
Reply
  • CGICs cannot be inferred from HDL hence cannot be 'uninferred'. You can indeed do 'clock_gating remove' and then rely on them being added again but I believe change_link is a better approach. Note change_link can relink to a module/subdesign so if your library does not have one, you would have to create a module/subdesign for it using latches/or/etc.

    gh-
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