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LVS Calibre check fail

nhanle

Hi all,

I ran a design use EDI, and there is no short violations when checking with EDI tool.

But, when checking LVS by Calibre, there are many Discrepancy in LVS report. A part of report is below:

Error: Different numbers of nets (see below).
Error: Different numbers of instances (see below).
Error: Connectivity errors.
Error: Instances of different types or subtypes were matched.
Error: Property errors.
Warning: Ambiguity points were found and resolved arbitrarily.

LAYOUT CELL NAME: pzqcal_fsm
SOURCE CELL NAME: pzqcal_fsm

--------------------------------------------------------------------------------------------------------------

INITIAL NUMBERS OF OBJECTS
--------------------------

                          Layout             Source           Component Type
------                  ------                 --------------
Ports:               126                  126

Nets:                 6608               6601 *

Instances:        7180               7180 MN (4 pins)
                           7222               7222 MP (4 pins)
------ ------
Total Inst:         14402              14402

NUMBERS OF OBJECTS AFTER TRANSFORMATION
---------------------------------------

              Layout Source Component Type
------ ------ --------------
Ports:    126     126

Nets:     3187  3149 *

Instances: 541   340 * MN (4 pins)
                  397    259 * MP (4 pins)
                    123  140 * SPDW_2_1 (4 pins)
                    2      3* SPDW_2_1_1 (5 pins)
                   5        5 SPDW_2_2 (5 pins)

I check detailed report, and see there is no short violations (internal/external cell), I also include label for pin, power/ground, and also add filler cell/tap cell for desgin. 

The Discrepancy include instances, net. For example:

Discrepancy #59 in pzqcal_fsm

X3/X343/M5(11.630,31.795) MP(pch_mac)                    XU19677/MM5 MP(pch_mac)
g: X3/348                                                                                g: n_342
d: X3/449                                                                                ** no similar net **
b: X3/449                                                                                ** no similar net **
** X3/388 **                                                                           d: n_500
** VDD **                                                                                b: VDD

I tried 3 days, but no results :(. Could you help me, please ?

Parents
  • This is very difficult to debug without knowing anything about the design. Did you run verifyConnectivity in EDI? You said you had no shorts, but that is a verifyGeometry check. You need to make sure you also have no opens.
Reply
  • This is very difficult to debug without knowing anything about the design. Did you run verifyConnectivity in EDI? You said you had no shorts, but that is a verifyGeometry check. You need to make sure you also have no opens.
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