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clock tree synthesis

Hello all,

When designing the clock tree for a design in SoC Encounter, can I specify certain clock delays for certain gates ? (for example I need the clock of gate x to rise after 0.2ns from the I/O clock pin rise). Is it possible to do this in the clock tree specification file ?

Thanks

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Kari over 8 years ago

you don't say if you're using CCOpt or the the old CTS. Either way, you can start out by telling the tool to balance these, but create a "macro delay" of the one that you want to be skewed out a bit.
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Kari over 8 years ago

you don't say if you're using CCOpt or the the old CTS. Either way, you can start out by telling the tool to balance these, but create a "macro delay" of the one that you want to be skewed out a bit.
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