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clock tree synthesis

oAwad
oAwad over 8 years ago

Hello all,

When designing the clock tree for a design in SoC Encounter, can I specify certain clock delays for certain gates ? (for example I need the clock of gate x to rise after 0.2ns from the I/O clock pin rise). Is it possible to do this in the clock tree specification file ? 

Thanks

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  • oAwad
    oAwad over 8 years ago

    I'm using the old CTS. What I found in the manual related to the "Macro delay" is this command:

    Macromodel pin lefPinName maxRiseDelay minRiseDelay maxFallDelay minFallDelay inputCap


    please confirm if this is what you mean. I need a delay of 0.2 ns in a special net so here is what I do:

    I create a scheduling file and add the following command to it (I'm not sure I'm setting the values correctly. Should I set the fall delays equal to the rise delays ?.....I need the whole clock to be delayed with ~0.2 ns)

    Macromodel clk_i__L5_N837 CK 0.3n 0.2n 0 0 0.9497f

    and then I set the scheduling file in the configuration file of the tool.

    and I add these two commands to my script file: 

    setOptMode -usefulSkew true
    optDesign -preCTS

     

    Is what I'm doing correct ?

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  • Kari
    Kari over 7 years ago in reply to oAwad

    Here's a sample command from an old script:

    MacroModel pin macro1/clk 300ps 300ps 300ps 300p 35fF

    I wouldn't put 0 for the fall delays. Use the same numbers as the rise.

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  • Kari
    Kari over 7 years ago in reply to oAwad

    Here's a sample command from an old script:

    MacroModel pin macro1/clk 300ps 300ps 300ps 300p 35fF

    I wouldn't put 0 for the fall delays. Use the same numbers as the rise.

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