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constraints file

Could any one please help me how to find the post layout delay of a full adder circuit?

I am working with digital cadence and when i try to get the post layout delay, the report is shown as "NO CONSTRAINED TIMING PATHS FOUND"

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Edouardfr over 6 years ago

1- Which command are you using?

2- Is this specific path constrained in your SDC file?

3- Did you try to use the -unconstrained option in your report_timing command?
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Edouardfr over 6 years ago

1- Which command are you using?

2- Is this specific path constrained in your SDC file?

3- Did you try to use the -unconstrained option in your report_timing command?
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Rahila over 6 years ago in reply to Edouardfr

im using the command report_timing to generate the post layout delay report... but the message is as i said..

even the synthesis timing report says that the design is unconstrained. since the design donot have a clk signal, what should be included in the constraints file?

i didnt use the unconstrained option in the command report_timing... could you please share how to use it?
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Edouardfr over 6 years ago in reply to Rahila

During synthesis, you can sue some commands like: set_max_delay , to constraint the delay between your input and outputs.

For STA, try using the command: report_timing -unconstrained
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Rahila over 6 years ago in reply to Edouardfr

ok sir.

thank you.
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