Direction of VDD/VSS (inout vs input)

What is the reason that power/ground ports that are added in the physical implementation flow have direction "inout" instead of "input"?  Is there a way to force them to be "input" instead without running some post-processing code?

a simple example is starting with something like this out of synthesis:

module mycell(A, Y);

    input A;

    output Y;

    INVX1 myinst(.A (A), .Y (Y));

endmodule

Then using things like this in the physical place/route:

set init_pwr_net "VDD"
set init_gnd_net "VSS"

globalNetConnect VSS -type pgpin -pin VSS -all
globalNetConnect VDD -type pgpin -pin VDD -all

and ending up with

module mycell(A, Y, VDD, VSS);

    input A;

    output Y;

    inout VDD;  // WHY INOUT

    inout VSS;  // WHY INOUT

    INVX1 myinst(.A (A), .Y (Y), .VDD(VDD), .VSS(VSS));

endmodule

The reason I care is in mixed signal sims (AMS) or even DMS sims, I want to avoid any possibility of bi-directional connect modules whenever possible.  To that end, I'd like to be able to simulate the post-physical design (that includes power/ground) but with those defined as "input" instead of "inout".