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HOLD VIOLATIONS AFTER SIGN OFF STAGE

amssshubham

Hello All,

I am doing digital synthesis for a type 2 digital Cdr at 500MHz in the 65nm gp process. At the end of postroute I don't get any setup or hold violations in my design.
But after timeDesign -signoff, I get a lot of violations in the hold path.
Initially, I was getting setup violations. But when I gave the control registers ( which will be controlled externally through spi) a hard courted value on reset, it got resolved.
But I am unable to understand why hold violations are coming.
Going through the timing report, I observed that the hold violations begin from reset or control bits (which will be controlled externally). Reset is asynchronous in nature. Is there something we need to define for static bits ( in the sense that they will be externally controlled inputs via spi).
Please let me know how I can resolve the issue. I am attaching a violation for your reference.

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