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Synthesizing Specific Gates in Cadence Genus

SR202412023415

Hello Cadence Community,

I'm working on a flattened netlist in Cadence Genus for a design and would like to apply targeted synthesis optimizations to a specific list of gates (e.g., g1234, g5678) while keeping the rest of the design unchanged. Is it possible to synthesize or optimize only these gates, and if so, how can I achieve this?

My current synthesis script uses commands like syn_generic, syn_map, and syn_opt, but these seem to reprocess the entire design, which I want to avoid. I'm using the NangateOpenCellLibrary_slow_ccs.lib library and have a list of gate names. Ideally, I'd like to apply optimizations such as using different cell types or adjusting attributes only for these gates.

Any guidance on commands (e.g., set_attr, incremental synthesis) or script modifications would be greatly appreciated. Thank you!

Best regards

Parents

  • # Mark all cells dont_touch
    set_dont_touch [get_cells *]

    # Clear dont_touch on target gates only
    foreach gate {g1234 g5678} {
    set_dont_touch -clear [get_cells $gate]
    }

    # Optionally set mapping constraints on those gates
    set_map_cell -inst g1234 new_cell_type1
    set_map_cell -inst g5678 new_cell_type2

    # Run incremental optimization (only for gates without dont_touch)
    syn_opt -incremental
    syn_map -incremental

    # Optionally run further incremental steps
    syn_check       

    You can try above steps 

Reply

  • # Mark all cells dont_touch
    set_dont_touch [get_cells *]

    # Clear dont_touch on target gates only
    foreach gate {g1234 g5678} {
    set_dont_touch -clear [get_cells $gate]
    }

    # Optionally set mapping constraints on those gates
    set_map_cell -inst g1234 new_cell_type1
    set_map_cell -inst g5678 new_cell_type2

    # Run incremental optimization (only for gates without dont_touch)
    syn_opt -incremental
    syn_map -incremental

    # Optionally run further incremental steps
    syn_check       

    You can try above steps 

Children
  • in reply to Frontend designer rr

    Thanks for your reply. I faced couple of questions. 
    First, the "-clear" was not a valid option for me an I needed to use the following command, and I wanted to ensure it's still correct:


    # set_dont_touch -help
    set_dont_touch [get_cells *]
    set_dont_touch [get_cells {g372734 g372735 g372736 g372737}] false
    Also, set_map_cell was not a valid command for me and I needed to comment it out.

    Additionally, "    syn_map" does not have -incremental option for me.

    After doing all these steps, when I checked the synthesized design, I realized that the re-synthesized netlist did not change at all.

    I would appreciate your help in advance.

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