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How to Compile System Verilog

System Verilog

Hi,

I use ncverilog: 05.70-s015: (c) Copyright 1995-2007 Cadence Design Systems, Inc.

TOOL:   ncverilog       05.70-s015:

and foll switches

    -update
    +access+r
    +sv31a

I egt the foll errs

class mem_base_object;
    |
ncvlog: *E,EXPMPA (../models/mem_base_object.sv,3|4): expecting the keyword 'module', 'macromodule' or 'primitive'[A.1].
(`include file: ../models/mem_base_object.sv | line 3, `include file: ../models/memory_top.sv line 3, file: ../tb/memory_tb.sv line 4)

  mem_txgen txgen;
                |
ncvlog: *E,ILLPDL (../models/memory_top.sv,11|16): Mixing of ansi & non-ansi style port declaration is not legal.
(`include file: ../models/memory_top.sv line 11, file: ../tb/memory_tb.sv line 4)
  mem_scoreboard sb;

pls let me know a solution

Thanks

Chandra

Force10 Networks Inc, SJC

Parents

  • The current version of NC-Verilog is IUS81-s006. Therefore, the version you are using is quite old and may be lacking some of the construct support that you require. I definitely recommend installing a later release.

    For your current issue, I'm guessing that you have your class definition outside of a module or package which be considered the "compilation unit scope". This is not supported until IUS62. Move your class definition inside of your module and see if that removes the problem for IUS57. 

    Tim

Reply

  • The current version of NC-Verilog is IUS81-s006. Therefore, the version you are using is quite old and may be lacking some of the construct support that you require. I definitely recommend installing a later release.

    For your current issue, I'm guessing that you have your class definition outside of a module or package which be considered the "compilation unit scope". This is not supported until IUS62. Move your class definition inside of your module and see if that removes the problem for IUS57. 

    Tim

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