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How to Compile System Verilog

System Verilog

Hi,

I use ncverilog: 05.70-s015: (c) Copyright 1995-2007 Cadence Design Systems, Inc.

TOOL:   ncverilog       05.70-s015:

and foll switches

    -update
    +access+r
    +sv31a

I egt the foll errs

class mem_base_object;
    |
ncvlog: *E,EXPMPA (../models/mem_base_object.sv,3|4): expecting the keyword 'module', 'macromodule' or 'primitive'[A.1].
(`include file: ../models/mem_base_object.sv | line 3, `include file: ../models/memory_top.sv line 3, file: ../tb/memory_tb.sv line 4)

  mem_txgen txgen;
                |
ncvlog: *E,ILLPDL (../models/memory_top.sv,11|16): Mixing of ansi & non-ansi style port declaration is not legal.
(`include file: ../models/memory_top.sv line 11, file: ../tb/memory_tb.sv line 4)
  mem_scoreboard sb;

pls let me know a solution

Thanks

Chandra

Force10 Networks Inc, SJC

Parents

  • Hi All,

     I am trying to run systemverilog files using :

    irun -f filelist . 

    irun: 10.20-p008: (c) Copyright 1995-2010 Cadence Design Systems, Inc.
    TOOL: irun 10.20-p008: Started on Oct 23, 2012 at 09:54:13 IST
    irun
     -f filelist
      Globals.sv
      rtl.sv
      interface.sv
      top.sv
      Packet.sv
      Driver.sv
      Receiver.sv
      Coverage.sv
      Scoreboard.sv
      Environemnt.sv
      testcase.sv
    file: Globals.sv
    file: rtl.sv
    file: interface.sv
    file: top.sv
    file: Packet.sv
    file: Driver.sv
    file: Receiver.sv
    file: Coverage.sv
    file: Scoreboard.sv
    file: Environemnt.sv
    file: testcase.sv
      Caching library 'worklib' ....... Done
     Elaborating the design hierarchy:
     Top level design units:
      $unit_0x04bbcec2
      top
      output_intf[0].cb.read    <= 0;
                |
    ncelab: *E,ASNUSE (./Environemnt.sv,56|12): Illegal use of a bit-select, part-select, member-select or mda element [9.3.1(IEEE)].
      output_intf[1].cb.read    <= 0;
                |
    ncelab: *E,ASNUSE (./Environemnt.sv,57|12): Illegal use of a bit-select, part-select, member-select or mda element [9.3.1(IEEE)].
      output_intf[2].cb.read    <= 0;
                |
    ncelab: *E,ASNUSE (./Environemnt.sv,58|12): Illegal use of a bit-select, part-select, member-select or mda element [9.3.1(IEEE)].
      output_intf[3].cb.read    <= 0;
                |
    ncelab: *E,ASNUSE (./Environemnt.sv,59|12): Illegal use of a bit-select, part-select, member-select or mda element [9.3.1(IEEE)].
    irun: *E,ELBERR: Error during elaboration (status 1), exiting.
    TOOL: irun 10.20-p008: Exiting on Oct 23, 2012 at 09:54:15 IST  (total: 00:00:02)

     

    -------------------------------------------------

    Environemnt.sv  has following:

    class Environment ;

    　

    virtual mem_interface.MEM mem_intf ;

    virtual input_interface.IP input_intf ;

    virtual output_interface.OP output_intf[4] ;

     

    Driver drvr;

    Receiver rcvr[4];

    Scoreboard sb;

    mailbox drvr2sb ;

    mailbox rcvr2sb ;

    function new(virtual mem_interface.MEM mem_intf_new ,

    virtual input_interface.IP input_intf_new ,

    virtual output_interface.OP output_intf_new[4] );

    this.mem_intf = mem_intf_new ;

    this.input_intf = input_intf_new ;

    this.output_intf = output_intf_new ;

    $display(" %0d : Environemnt : created env object",$time);

    endfunction : new

    function void build();

    $display(" %0d : Environemnt : start of build() method",$time);

    drvr2sb = new();

    rcvr2sb = new();

    sb = new(drvr2sb,rcvr2sb);

    drvr= new(input_intf,drvr2sb);

    foreach(rcvr[i])

    rcvr[i]= new(output_intf[i],rcvr2sb);

    $display(" %0d : Environemnt : end of build() method",$time);

    endfunction : build

    task reset();

    $display(" %0d : Environemnt : start of reset() method",$time);

    // Drive all DUT inputs to a known state

    mem_intf.cb.mem_data <= 0;

    mem_intf.cb.mem_add <= 0;

    mem_intf.cb.mem_en <= 0;

    mem_intf.cb.mem_rd_wr <= 0;

    input_intf.cb.data_in <= 0;

    input_intf.cb.data_status <= 0;

    output_intf[0].cb.read <= 0;

    output_intf[1].cb.read <= 0;

    output_intf[2].cb.read <= 0;

    output_intf[3].cb.read <= 0;

     

    // Reset the DUT

    input_intf.reset <= 1;

    repeat (4) @ input_intf.clock;

    input_intf.reset <= 0;

     

    $display(" %0d : Environemnt : end of reset() method",$time);

    endtask : reset

     

     

     Please help me to rectify these errors

    Thanks and regards,

    Chandan

Reply

  • Hi All,

     I am trying to run systemverilog files using :

    irun -f filelist . 

    irun: 10.20-p008: (c) Copyright 1995-2010 Cadence Design Systems, Inc.
    TOOL: irun 10.20-p008: Started on Oct 23, 2012 at 09:54:13 IST
    irun
     -f filelist
      Globals.sv
      rtl.sv
      interface.sv
      top.sv
      Packet.sv
      Driver.sv
      Receiver.sv
      Coverage.sv
      Scoreboard.sv
      Environemnt.sv
      testcase.sv
    file: Globals.sv
    file: rtl.sv
    file: interface.sv
    file: top.sv
    file: Packet.sv
    file: Driver.sv
    file: Receiver.sv
    file: Coverage.sv
    file: Scoreboard.sv
    file: Environemnt.sv
    file: testcase.sv
      Caching library 'worklib' ....... Done
     Elaborating the design hierarchy:
     Top level design units:
      $unit_0x04bbcec2
      top
      output_intf[0].cb.read    <= 0;
                |
    ncelab: *E,ASNUSE (./Environemnt.sv,56|12): Illegal use of a bit-select, part-select, member-select or mda element [9.3.1(IEEE)].
      output_intf[1].cb.read    <= 0;
                |
    ncelab: *E,ASNUSE (./Environemnt.sv,57|12): Illegal use of a bit-select, part-select, member-select or mda element [9.3.1(IEEE)].
      output_intf[2].cb.read    <= 0;
                |
    ncelab: *E,ASNUSE (./Environemnt.sv,58|12): Illegal use of a bit-select, part-select, member-select or mda element [9.3.1(IEEE)].
      output_intf[3].cb.read    <= 0;
                |
    ncelab: *E,ASNUSE (./Environemnt.sv,59|12): Illegal use of a bit-select, part-select, member-select or mda element [9.3.1(IEEE)].
    irun: *E,ELBERR: Error during elaboration (status 1), exiting.
    TOOL: irun 10.20-p008: Exiting on Oct 23, 2012 at 09:54:15 IST  (total: 00:00:02)

     

    -------------------------------------------------

    Environemnt.sv  has following:

    class Environment ;

    　

    virtual mem_interface.MEM mem_intf ;

    virtual input_interface.IP input_intf ;

    virtual output_interface.OP output_intf[4] ;

     

    Driver drvr;

    Receiver rcvr[4];

    Scoreboard sb;

    mailbox drvr2sb ;

    mailbox rcvr2sb ;

    function new(virtual mem_interface.MEM mem_intf_new ,

    virtual input_interface.IP input_intf_new ,

    virtual output_interface.OP output_intf_new[4] );

    this.mem_intf = mem_intf_new ;

    this.input_intf = input_intf_new ;

    this.output_intf = output_intf_new ;

    $display(" %0d : Environemnt : created env object",$time);

    endfunction : new

    function void build();

    $display(" %0d : Environemnt : start of build() method",$time);

    drvr2sb = new();

    rcvr2sb = new();

    sb = new(drvr2sb,rcvr2sb);

    drvr= new(input_intf,drvr2sb);

    foreach(rcvr[i])

    rcvr[i]= new(output_intf[i],rcvr2sb);

    $display(" %0d : Environemnt : end of build() method",$time);

    endfunction : build

    task reset();

    $display(" %0d : Environemnt : start of reset() method",$time);

    // Drive all DUT inputs to a known state

    mem_intf.cb.mem_data <= 0;

    mem_intf.cb.mem_add <= 0;

    mem_intf.cb.mem_en <= 0;

    mem_intf.cb.mem_rd_wr <= 0;

    input_intf.cb.data_in <= 0;

    input_intf.cb.data_status <= 0;

    output_intf[0].cb.read <= 0;

    output_intf[1].cb.read <= 0;

    output_intf[2].cb.read <= 0;

    output_intf[3].cb.read <= 0;

     

    // Reset the DUT

    input_intf.reset <= 1;

    repeat (4) @ input_intf.clock;

    input_intf.reset <= 0;

     

    $display(" %0d : Environemnt : end of reset() method",$time);

    endtask : reset

     

     

     Please help me to rectify these errors

    Thanks and regards,

    Chandan

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