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How to Compile System Verilog

System Verilog

Hi,

I use ncverilog: 05.70-s015: (c) Copyright 1995-2007 Cadence Design Systems, Inc.

TOOL:   ncverilog       05.70-s015:

and foll switches

    -update
    +access+r
    +sv31a

I egt the foll errs

class mem_base_object;
    |
ncvlog: *E,EXPMPA (../models/mem_base_object.sv,3|4): expecting the keyword 'module', 'macromodule' or 'primitive'[A.1].
(`include file: ../models/mem_base_object.sv | line 3, `include file: ../models/memory_top.sv line 3, file: ../tb/memory_tb.sv line 4)

  mem_txgen txgen;
                |
ncvlog: *E,ILLPDL (../models/memory_top.sv,11|16): Mixing of ansi & non-ansi style port declaration is not legal.
(`include file: ../models/memory_top.sv line 11, file: ../tb/memory_tb.sv line 4)
  mem_scoreboard sb;

pls let me know a solution

Thanks

Chandra

Force10 Networks Inc, SJC

Parents

  • Using IUS versions 10.2, 11.1, and 12.1, I had no problem in running this code:

    class Environment ;

      virtual output_interface.OP output_intf[2] ;

      

      function new( virtual output_interface.OP output_intf_new[2] );

        this.output_intf = output_intf_new ;

        $display(" %0d : Environemnt : created env object",$time);

        reset ;

      endfunction : new

     

      task reset();

        $display(" %0d : Environemnt : start of reset() method",$time);

        // Drive all DUT inputs to a known state

        output_intf[0].cb.read <= 0;

        output_intf[1].cb.read <= 0;

        $display(" %0d : Environemnt : end of reset() method",$time);

      endtask : reset

    endclass : Environment

    interface output_interface();

      logic    read;

      logic    clock;

      clocking cb@(posedge clock);

        default input #1 output #1;

        output    read;

      endclocking

      modport OP(clocking cb,input clock);

    endinterface

     

    module top;

      output_interface o[2]();

      Environment env = new(o);

    endmodule

    Do you get an error if you run this code? If not, what are you doing differently?

    Tim

Reply

  • Using IUS versions 10.2, 11.1, and 12.1, I had no problem in running this code:

    class Environment ;

      virtual output_interface.OP output_intf[2] ;

      

      function new( virtual output_interface.OP output_intf_new[2] );

        this.output_intf = output_intf_new ;

        $display(" %0d : Environemnt : created env object",$time);

        reset ;

      endfunction : new

     

      task reset();

        $display(" %0d : Environemnt : start of reset() method",$time);

        // Drive all DUT inputs to a known state

        output_intf[0].cb.read <= 0;

        output_intf[1].cb.read <= 0;

        $display(" %0d : Environemnt : end of reset() method",$time);

      endtask : reset

    endclass : Environment

    interface output_interface();

      logic    read;

      logic    clock;

      clocking cb@(posedge clock);

        default input #1 output #1;

        output    read;

      endclocking

      modport OP(clocking cb,input clock);

    endinterface

     

    module top;

      output_interface o[2]();

      Environment env = new(o);

    endmodule

    Do you get an error if you run this code? If not, what are you doing differently?

    Tim

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