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How to Compile System Verilog

System Verilog

Hi,

I use ncverilog: 05.70-s015: (c) Copyright 1995-2007 Cadence Design Systems, Inc.

TOOL:   ncverilog       05.70-s015:

and foll switches

    -update
    +access+r
    +sv31a

I egt the foll errs

class mem_base_object;
    |
ncvlog: *E,EXPMPA (../models/mem_base_object.sv,3|4): expecting the keyword 'module', 'macromodule' or 'primitive'[A.1].
(`include file: ../models/mem_base_object.sv | line 3, `include file: ../models/memory_top.sv line 3, file: ../tb/memory_tb.sv line 4)

  mem_txgen txgen;
                |
ncvlog: *E,ILLPDL (../models/memory_top.sv,11|16): Mixing of ansi & non-ansi style port declaration is not legal.
(`include file: ../models/memory_top.sv line 11, file: ../tb/memory_tb.sv line 4)
  mem_scoreboard sb;

pls let me know a solution

Thanks

Chandra

Force10 Networks Inc, SJC

Parents

  • Thanks Tim. I am still getting the same error. I ran this code (modified calling reset task from run task )

    class Environment ;

      virtual output_interface.OP output_intf[2] ;

      function new( virtual output_interface.OP output_intf_new[2] );

        this.output_intf = output_intf_new ;

        $display(" %0d : Environemnt : created env object",$time);

      endfunction : new

      task reset();

        $display(" %0d : Environemnt : start of reset() method",$time);

        // Drive all DUT inputs to a known state

        output_intf[0].cb.read <= 0;

        output_intf[1].cb.read <= 0;

        $display(" %0d : Environemnt : end of reset() method",$time);

      endtask : reset

    task run();
            reset();
    endtask : run

    endclass : Environment


    interface output_interface(input bit clock);

      logic    read;

     clocking cb@(posedge clock);

        default input #1 output #1;

        output    read;

      endclocking

      modport OP(clocking cb,input clock);

    endinterface

     

    module top;

    bit clock;

    initial
            forever #10 clock = ~clock;

      output_interface o[2](clock);

      Environment env = new(o);

    endmodule
    --------------------------------------------

    the log file reads:

    irun: 10.20-p008: (c) Copyright 1995-2010 Cadence Design Systems, Inc.
    TOOL:   irun    10.20-p008: Started on Oct 26, 2012 at 10:58:10 IST
    irun
            tpylant.sv
    file: tpylant.sv
            interface worklib.output_interface:sv
                    errors: 0, warnings: 0
            module worklib.top:sv
                    errors: 0, warnings: 0
                    Caching library 'worklib' ....... Done
            Elaborating the design hierarchy:
            Top level design units:
                    $unit_0x7631bed7
                    top
        output_intf[0].cb.read <= 0;
                  |
    ncelab: *E,ASNUSE (./tpylant.sv,21|14): Illegal use of a bit-select, part-select, member-select or mda element [9.3.1(IEEE)].
        output_intf[1].cb.read <= 0;
                  |
    ncelab: *E,ASNUSE (./tpylant.sv,23|14): Illegal use of a bit-select, part-select, member-select or mda element [9.3.1(IEEE)].
    irun: *E,ELBERR: Error during elaboration (status 1), exiting.
    TOOL:   irun    10.20-p008: Exiting on Oct 26, 2012 at 10:58:11 IST  (total: 00:00:01)

    Is this problem due to tool version ?

    Regards,

    Chandan

     

     

Reply

  • Thanks Tim. I am still getting the same error. I ran this code (modified calling reset task from run task )

    class Environment ;

      virtual output_interface.OP output_intf[2] ;

      function new( virtual output_interface.OP output_intf_new[2] );

        this.output_intf = output_intf_new ;

        $display(" %0d : Environemnt : created env object",$time);

      endfunction : new

      task reset();

        $display(" %0d : Environemnt : start of reset() method",$time);

        // Drive all DUT inputs to a known state

        output_intf[0].cb.read <= 0;

        output_intf[1].cb.read <= 0;

        $display(" %0d : Environemnt : end of reset() method",$time);

      endtask : reset

    task run();
            reset();
    endtask : run

    endclass : Environment


    interface output_interface(input bit clock);

      logic    read;

     clocking cb@(posedge clock);

        default input #1 output #1;

        output    read;

      endclocking

      modport OP(clocking cb,input clock);

    endinterface

     

    module top;

    bit clock;

    initial
            forever #10 clock = ~clock;

      output_interface o[2](clock);

      Environment env = new(o);

    endmodule
    --------------------------------------------

    the log file reads:

    irun: 10.20-p008: (c) Copyright 1995-2010 Cadence Design Systems, Inc.
    TOOL:   irun    10.20-p008: Started on Oct 26, 2012 at 10:58:10 IST
    irun
            tpylant.sv
    file: tpylant.sv
            interface worklib.output_interface:sv
                    errors: 0, warnings: 0
            module worklib.top:sv
                    errors: 0, warnings: 0
                    Caching library 'worklib' ....... Done
            Elaborating the design hierarchy:
            Top level design units:
                    $unit_0x7631bed7
                    top
        output_intf[0].cb.read <= 0;
                  |
    ncelab: *E,ASNUSE (./tpylant.sv,21|14): Illegal use of a bit-select, part-select, member-select or mda element [9.3.1(IEEE)].
        output_intf[1].cb.read <= 0;
                  |
    ncelab: *E,ASNUSE (./tpylant.sv,23|14): Illegal use of a bit-select, part-select, member-select or mda element [9.3.1(IEEE)].
    irun: *E,ELBERR: Error during elaboration (status 1), exiting.
    TOOL:   irun    10.20-p008: Exiting on Oct 26, 2012 at 10:58:11 IST  (total: 00:00:01)

    Is this problem due to tool version ?

    Regards,

    Chandan

     

     

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