Questions about IFV - PLS Help! - New to IFV

 Hi Alexlop,

 You might want to get in touch with your Cadence support person for some IFV help. IFV has good support and they should help you get started on your formal verfication adventure.

As far as your question goes - it looks like you are trying to shape a specific input stimulus through assumptions. This is a common mistake made by beginners who are familiar with simulation environments (I should know, I was one). Assumptions are used to inform the tool of the DUT's external environment - it is typically not a good idea to use assumptions to specify a directed input sequence like you are trying to do.

Now, I think your intent is to do some design exploration. This is good and a cool application of IFV. To do this sort of thing - setup assumptions on your design inputs that capture the protocols for those inputs. For instance, if your design uses an AHB interface, then write a set of AHB assumptions so that the tool considers only valid AHB input sequences.

Next, if you want to see if a specific sequence of events can occur, you write a cover statement like so -

coverS7: cover {INPUT1 ; !INPUT1 ; INPUT2 ; current_state = 7} @(posedge clk);

If this sequence is possible, within the set of assumptions on the design, then the tool will show you a trace demonstrating how this can happen. The nice thing about the trace is that if your inputs are not behaving as you (and the design) expect them to, then you can add more input assumptions. If it is not possible for the sequence to occur, then the tool will say that the cover Failed.

Finally, this is the right forum for this type of question and you should find an adequate level of support here. Let me know if this helped.

 Further, if you wanted the second term of the cover to be"nevermind" then you can write it like so -

s7: cover  {INPUT1; true; INPUT2; current_state= 7} @(posedge clk);

Thank you FormalGuy.

I haven't tried it yet because I am out of my office for a few days, but I try it as soon as I get back.

 Thanks FormalGuy! Everything worked just like I ment.

Anyway for those who have no idea what is PSL and how to use it, I've found a nice tutorial: http://www.project-veripage.com/psl_tutorial_1.php

(I find PSL easeir to lern than OVL)

 HELLO GUYS!

I have another question.

I am trying to tell IFV to assume that a packet starts with 'sop' and ends with 'eop' so that it will not look through options like 'eop' without 'sop' and 'sop' followed by 'sop'.

 I tried the following :

assume_packet_length : assume always ({sop} => {(!sop && !eop)[*4:100];eop}) @ (posedge clk_l);

but IFV doesn't like this, it shows vacuity problem.

What is the reason for this and how can I solve this problem.

 Thanks!

Hi,

 I would strongly encourage you to contact your local AE.  We have a training that will answer your questions. In addition, our training labs include an example that has an sop/eop protocol.  My guess is you'll be able to take those assertions from the lab, learn how/why they work and drop them into your design at the same time as learning all the other goodness about IFV.

 My guess is that this will be the fastest route to getting you going.

 Thanks,

Chris

 Thanks ckomar.

I have another question (to all of you).

How can I check (if it is possible at all) that specific signal has or has not 'z' or 'x' values?

Thanks.

Hi Alex,

there is a built-in function in PSL and SVA: isunknown(<bit_vector>). It performs the check you are asking for. In IFV it will return false unless you configure IFV to evaluate Z on tristate signals.

Joerg.

Hi Guys,

       I  have one question. How can i check a combo module with the IFV. IFV ask for the clock.

let say there 2 input signals and 2 o/p's

IN1, IN2 , OUT1, OUT2

the o/p depends on the both inputs as shown below.

when ever (IN1 == x) && (IN2 == y) then (OUT1 == m) && (OUT == n)

 i had tried the following assertions.

Lable_1: assert propery

(

(IN1 == x) && (IN2 == y))  |-> ((OUT1 == m) && (OUT == n))

);

the above assertion gives the error that clock is not spsified

then i tried that

assert always

{

(IN1 == x) && (IN2 == y))  |-> ((OUT1 == m) && (OUT == n))

};

 the above assertion is not behaving in the intended way. please help me out

 Thanks

Sri

Hi Sri

I assume you want to describe the following property:

// psl p1: assert always ((IN1 == x) && (IN2 == y))  -> ((OUT1 == m) && (OUT == n));

Note the difference in the brackets ("()" for boolean and "{}" for sequences) and the implication operater "->" for booleans (rather than "|->" for sequences). The above syntax works without a clock. In SVA this is more difficult...

 Joerg.