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Questions about IFV - PLS Help! - New to IFV

alexlop

 Hi,

I am new to IFV (Formal Verifier), I've just started examining this tool a few days ago.

In our company I am the first one to lern it so I have nobody to ask for help but you guys!

 

Let's say I want to check some feature in the design.

I have a state machine and  INPUT1 is "1" for one clock cycle then another clock cycle (on which I don't care about the inputs) followed by third clock cycle on which  INPUT2 is "1, now I want to check if after this sequence can the state machine be at (let's say) "state_7".

First of all how can I  formulate the assumption for that kind of input sequence? I tried :

    sop_one_cycle : assume always {INPUT1} |-> {!INPUT1};
    short_packet : assume always {INPUT1} |-> {!INPUT2; INPUT2};

    coverS7 : cover {current_state == 7} @ (posedge clk);

but as I understood from "ifvuser.pdf", {!INPUT2; INPUT2} will couse to contradiction as the IFV checks for INPUT2 and !INPUT2 at the same cycle of clock. (However it showed no error message)

Anyway, how can I tell IFV that I want to check sequence of :INPUT1="1":nevermind:INPUT2="1":

Thanks!!!

P.S.

   If this is not the correct place to ask such a question please point me to the right forum.

 

Parents

  •  HELLO GUYS!

    I have another question.

    I am trying to tell IFV to assume that a packet starts with 'sop' and ends with 'eop' so that it will not look through options like 'eop' without 'sop' and 'sop' followed by 'sop'.

     I tried the following :

    assume_packet_length : assume always ({sop} => {(!sop && !eop)[*4:100];eop}) @ (posedge clk_l);

    but IFV doesn't like this, it shows vacuity problem.

    What is the reason for this and how can I solve this problem.

     Thanks!

Reply

  •  HELLO GUYS!

    I have another question.

    I am trying to tell IFV to assume that a packet starts with 'sop' and ends with 'eop' so that it will not look through options like 'eop' without 'sop' and 'sop' followed by 'sop'.

     I tried the following :

    assume_packet_length : assume always ({sop} => {(!sop && !eop)[*4:100];eop}) @ (posedge clk_l);

    but IFV doesn't like this, it shows vacuity problem.

    What is the reason for this and how can I solve this problem.

     Thanks!

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