Conversion of an Integer port in VHDL to equivalent in Verilog

 Hi Sarvesh,

Just to be clear, you have a verilog module with an integer port and you are instantiating that verilog module in vhdl.  If that's the case, take a look at the example below and let me know if that helps.

verilog

-----------

module using_integer_port (clk, in1, out1);
input clk;
input  in1;
output out1;

wire [31:0] in1;
integer out1;

always @(posedge clk)
  out1 = in1;
endmodule
-------------------------

vhdl 

------------------------

library ieee;
use ieee.std_logic_1164.all;
entity test is
end test;

architecture vhdl of test is

component using_integer_port
       port (clk: in std_logic;
             in1: in std_logic_vector;
              out1: out std_logic_vector);
end component;
signal clk: std_logic := '0';
signal d: std_logic_vector (31 downto 0);
signal q: std_logic_vector (31 downto 0);

begin
    clk <= not clk after 20 ns;

    process begin
        wait for 3 ns;    
             d <= X"01000111";
        wait for 5 ns;
             d <= X"11000111";
        wait for 13 ns;
             d <= X"00011001";
    end process;
    inst:using_integer_port port map (clk, d, q);
end vhdl;

--------------

Hope that helps.

Best regards,

Mickey

Mickey said:

module using_integer_port (clk, in1, out1);

input clk;
input  in1;
output out1;

wire [31:0] in1;
integer out1;

always @(posedge clk)
  out1 = in1; // coding style-error, flipflop should be '<='

endmodule

As written, your Verilog-module has single bit-wide ports. I don't think Verilog-2001 allows module-ports to be specified as type integer.  (Parameters, function-args, and task-args can be formally specified integer.)

My VHDL is a bit rusty, but I'm guessing it's shorthand for a 32-bit signed integer?  If that's the case, you could try something like this:

`define fake_integer signed [31:0]

 

module v2001_using_integer_port (

  input wire clk,

  input wire `fake_integer in1,

  output reg `fake_integer out1

  );

always @(posedge clk)
  out1 <= in1;
endmodule