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Conversion of an Integer port in VHDL to equivalent in Verilog

Sarvesh

Hello,

I am using NC-VHDL and trying to port map a verilog file in the VHDL enviroment. I am not able to convert an integer port which is present in the original file. Is there any workaround for this in Verilog ? I have tried using [15:0] array also a [31:0] array but there is a compilation error as NCVHDL says it cannot find any equivalent matching datatype. Please help.

Regards,

Parents

  • Mickey said:
    module using_integer_port (clk, in1, out1);

    input clk;
    input  in1;
    output out1;

    wire [31:0] in1;
    integer out1;

    always @(posedge clk)
      out1 = in1; // coding style-error, flipflop should be '<='

    endmodule

     

    As written, your Verilog-module has single bit-wide ports. I don't think Verilog-2001 allows module-ports to be specified as type integer.  (Parameters, function-args, and task-args can be formally specified integer.)

     

    My VHDL is a bit rusty, but I'm guessing it's shorthand for a 32-bit signed integer?  If that's the case, you could try something like this:

    `define fake_integer signed [31:0]

     

    module v2001_using_integer_port (

      input wire clk,

      input wire `fake_integer in1,

      output reg `fake_integer out1

      );


    always @(posedge clk)
      out1 <= in1;
    endmodule

Reply

  • Mickey said:
    module using_integer_port (clk, in1, out1);

    input clk;
    input  in1;
    output out1;

    wire [31:0] in1;
    integer out1;

    always @(posedge clk)
      out1 = in1; // coding style-error, flipflop should be '<='

    endmodule

     

    As written, your Verilog-module has single bit-wide ports. I don't think Verilog-2001 allows module-ports to be specified as type integer.  (Parameters, function-args, and task-args can be formally specified integer.)

     

    My VHDL is a bit rusty, but I'm guessing it's shorthand for a 32-bit signed integer?  If that's the case, you could try something like this:

    `define fake_integer signed [31:0]

     

    module v2001_using_integer_port (

      input wire clk,

      input wire `fake_integer in1,

      output reg `fake_integer out1

      );


    always @(posedge clk)
      out1 <= in1;
    endmodule

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