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Profiling the runtime of SystemVerilog Assertions

danlarkin

Hi all,

I'm concerned that a collection of assertion based checkers that I'm using are causing a dramatic slow down in the run time of my simulation. My hunch is that  the widespread use of multiple internal variables in some of the assertions are using vast amounts of memory and are thus negatively impacting the run time of the overall simulation.

How do I go about debugging such an issue? For example, I remember hearing that Incisive 8.2 was to have the ability to profile assertions - however when I tried out 8.20-p001 (and added the -profile option) I don't seem to be getting any additional profile information in the profile logfile?

 Any pointers o0r recommendations would be most appreciated.

Thanks

Daniel 

Parents

  • Hi Daniel,

     You are correct. This feature was added in version 8.2. I just tried it on a simple testcase that I have and get the following in my ncprof.out.  Are you not seeing a section in the log file that looks something like this?

    ------------------------------------------------------------
    Assertion Summary Counts (15 hits, 28.8% of total)
    ------------------------------------------------------------
    %hits #hits  #inst  name
      7.7     4 [    1] input_Done_and_Gnt (assert stmt, file: ../vcomp/vcomp_arb.v, line: 27)
      3.8     2 [    1] output_GntA_then_Busy_overlaps_Done (assert stmt, file: ../vcomp/vcomp_arb.v, line: 65)
      3.8     2 [    1] output_Gnt_onehot0 (assert stmt, file: ../vcomp/vcomp_arb.v, line: 40)
      3.8     2 [    1] input_Gnt_eventually_Done (assert stmt, file: ../vcomp/vcomp_arb.v, line: 23)
      3.8     2 [    1] input_ReqB_and_GntB (assert stmt, file: ../vcomp/vcomp_arb.v, line: 17)
      3.8     2 [    1] input_ReqA_and_GntA (assert stmt, file: ../vcomp/vcomp_arb.v, line: 15)
      1.9     1 [    1] output_GntB_then_Busy_overlaps_Done (assert stmt, file: ../vcomp/vcomp_arb.v, line: 67)

    Chris

Reply

  • Hi Daniel,

     You are correct. This feature was added in version 8.2. I just tried it on a simple testcase that I have and get the following in my ncprof.out.  Are you not seeing a section in the log file that looks something like this?

    ------------------------------------------------------------
    Assertion Summary Counts (15 hits, 28.8% of total)
    ------------------------------------------------------------
    %hits #hits  #inst  name
      7.7     4 [    1] input_Done_and_Gnt (assert stmt, file: ../vcomp/vcomp_arb.v, line: 27)
      3.8     2 [    1] output_GntA_then_Busy_overlaps_Done (assert stmt, file: ../vcomp/vcomp_arb.v, line: 65)
      3.8     2 [    1] output_Gnt_onehot0 (assert stmt, file: ../vcomp/vcomp_arb.v, line: 40)
      3.8     2 [    1] input_Gnt_eventually_Done (assert stmt, file: ../vcomp/vcomp_arb.v, line: 23)
      3.8     2 [    1] input_ReqB_and_GntB (assert stmt, file: ../vcomp/vcomp_arb.v, line: 17)
      3.8     2 [    1] input_ReqA_and_GntA (assert stmt, file: ../vcomp/vcomp_arb.v, line: 15)
      1.9     1 [    1] output_GntB_then_Busy_overlaps_Done (assert stmt, file: ../vcomp/vcomp_arb.v, line: 67)

    Chris

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