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Verilog Name Collisions - irun v8.1

Dave123

I am trying to simulate a chip that consists of several DSP blocks with irun v8.1. The DSP blocks are written in a high level tool which then generates a verilog model for each block. Unfortunately, common names are used in DSP blocks for modules which are not functionally equivalent. As a result, the chip cannot be simulated properly at the top level. The simulator applies the last module compiled to each DSP block.

 Is there an easy way around this short of renaming all the sub-modules in the DSP block?

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  •  I haven't had time to try it for a Verilog design, but the irun option "-makelib" might work for this scenario. Simply use -makelib and -endlib to delimit the range of files that go into each DSP library, something like this:

    irun -makelib dsp1 rtl/dsp1/*.v -endlib -makelib dsp2 rtl/dsp2/*.v -endlib

     

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  •  I haven't had time to try it for a Verilog design, but the irun option "-makelib" might work for this scenario. Simply use -makelib and -endlib to delimit the range of files that go into each DSP library, something like this:

    irun -makelib dsp1 rtl/dsp1/*.v -endlib -makelib dsp2 rtl/dsp2/*.v -endlib

     

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