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SVA and IFV

natg9

Hello all

 Is IFV a stand alone tool using which we can write System Verilog Assertions and do a complete verification ?

or will i have to use an environment using some HVL and methodology to incorporate the SV Assertions.

 

thanks

Regards

natg

  • Hi natg.

    Yes, IFV allows you to do complete formal proofs (verification) of your design without needed an HDL testbench.
    You can use PSL, SVA and OVL assertions. Sometimes for complex problems it can help to add some simple RTL code to aid the assertion writing, and IFV supports that also.

    If you're interested in IFV, get in touch with your local Cadence team, who can arrange to help you try it out on a real design...

    Regards,

    Steve.

  • Hi Steve

    Thanks  for answering my query .

     

    I wish to know whether what you suggested about the local Cadence Team is a chargeable activity ?

     

    kindly revert with more details on the same

     

     

    Regards

    Girish

  • For the record, Girish and I took this discussion off-line...

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