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Gate Level simulation for Big(Huge) chip

Brodov Dmitriy

Hello!

I have the target of running the Gate Level (GTL) simulation for large chip.
The GTL simulation is very, very slow and impossible to debug in such conditions.

Is any one familiar with the solution to fast up the simulation:
It could be tools or some sort of hierarchy design/SDF, Netlist splitting and etc?

Thank you for the help ;-)

BR, Dima

 

  • Hi Dima.

    The laziest way to speed up netlist simulations is to use a hardware emulator like Palladium - it can run at MHz speeds with full debuggability, work with non-synthesisable testbenches and connect to the real world too. Emulation is a lot cheaper now than it was even just a few years ago, so it might be worth investigation.

    For NCSim simulation, you might try turning off any cell library timing checks (ncelab -notimingchecks).
    You should consider turning off as much of the simulation access as possible (no -access +RWC), or turn it on only for the blocks you might need to traces waves for.

    Splitting the netlist might be an option, certainly some people are doing that.
    Since you can elaborate multiple snapshots into a single INCA_libs library, you can elaborate a few different chip views, name each snapshot according to its purpose, then use "ncsim <snapshot_name>" to simulate the chosen design subset.

    Maybe some other readers have some other suggestions that work for them?

    Regards,
    Steve.

  • Steve, Thank you very much for your answer.


    Palladium sound interesting, but expensive ;-)
    Turning off all the timing checks is not such a good options since "timing checks" is one of issues that are not fully covered by STA.
    Right now i am checking the splitting of Netlist/SDF files and how the verification env. will handle it.


    If I will reach some new conclusion I will post them.

     

     

     

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