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Gate Level simulation for Big(Huge) chip

Brodov Dmitriy

Hello!

I have the target of running the Gate Level (GTL) simulation for large chip.
The GTL simulation is very, very slow and impossible to debug in such conditions.

Is any one familiar with the solution to fast up the simulation:
It could be tools or some sort of hierarchy design/SDF, Netlist splitting and etc?

Thank you for the help ;-)

BR, Dima

 

Parents

  • Steve, Thank you very much for your answer.


    Palladium sound interesting, but expensive ;-)
    Turning off all the timing checks is not such a good options since "timing checks" is one of issues that are not fully covered by STA.
    Right now i am checking the splitting of Netlist/SDF files and how the verification env. will handle it.


    If I will reach some new conclusion I will post them.

     

     

     

Reply

  • Steve, Thank you very much for your answer.


    Palladium sound interesting, but expensive ;-)
    Turning off all the timing checks is not such a good options since "timing checks" is one of issues that are not fully covered by STA.
    Right now i am checking the splitting of Netlist/SDF files and how the verification env. will handle it.


    If I will reach some new conclusion I will post them.

     

     

     

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