SystemVerilog queue of classes

Hi all,

I try using a queue of classes but there seems to be a problem when trying to read an item from the queue. I always receives only the last item pushed into the queue... I built the following test case:

code starts here: 

module tst_case_queue_of_class ();

class cls_tmp;

    byte tmp1;
    byte tmp2;
   
endclass

cls_tmp cls_q[$];
cls_tmp in_item = new();
cls_tmp out_item= new();

initial
begin
    #10;
    in_item.tmp1 = 8'h00;
    in_item.tmp2 = 8'h01;
    cls_q.push_back(in_item);

    #10;
    in_item.tmp1 = 8'h01;
    in_item.tmp2 = 8'h02;
    cls_q.push_back(in_item);

    #10;
    in_item.tmp1 = 8'h03;
    in_item.tmp2 = 8'h04;
    cls_q.push_back(in_item);
                                
    #10;
    in_item.tmp1 = 8'h05;       
    in_item.tmp2 = 8'h06;
    cls_q.push_back(in_item);

    for (int i = 0; i < cls_q.size(); i++)
    begin
        $display("index= %1d: tmp1=0x%2h, tmp2=0x%2h",i ,cls_q[i].tmp1 ,cls_q[i].tmp2);
    end // for (int i = 0; i < cls_q.size(); i++)

    repeat(4)
    begin
        out_item = cls_q.pop_front();
        $display("q_size= %1d: tmp1=0x%2h, tmp2=0x%2h",cls_q.size() ,out_item.tmp1 ,out_item.tmp2);       
    end // repeat(4)
   
end // initial

endmodule

Results of the simulation:

index= 0: tmp1=0x05, tmp2=0x06
index= 1: tmp1=0x05, tmp2=0x06
index= 2: tmp1=0x05, tmp2=0x06
index= 3: tmp1=0x05, tmp2=0x06
q_size= 3: tmp1=0x05, tmp2=0x06
q_size= 2: tmp1=0x05, tmp2=0x06
q_size= 1: tmp1=0x05, tmp2=0x06
q_size= 0: tmp1=0x05, tmp2=0x06

code and simulation results stop here

What is the problem with queue of classes? By the way, when trying to use a queue of structs I receive a compilation error...

Thanks,

Flanter