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system verilog compilation with verilog files

anshman

I am compiling my system verilog based test bench, the design uses some old modules which have reserve keywords that are not reserved for verilog e.g. program, do, type etc. now when I am compiling it is showing that keywords used, is there any other way to resolve this problem rahter than changing the variable names, can I tell the ncverilog simulator that these are verilog files and hence dont check for the sv keywords in those files. 

 Regards

Anshuman 

  • Hi Anshuman,

    The easiest way to attack this issue is to give your systemverilog files a separate extension (.sv, for example) than your regular verilog files (use .v for regular verilog) and then use irun in place of ncverilog when executing the simulation.  irun accomodates systemverilog and regular verilog compiling by calling the appropriate compiler based on the extension of the file.  So if you have a systemverilog file named myfile.sv and a regular verilog file named somefile.v, you would execute them with irun as follows.

    irun somefile.v adifferentfile.sv

    btw, irun as a default recognizes .sv as a systemverilog file type and .v as regular verilog.

    Hope that helps.

    Best regards,

    Mickey

  • woops...  messed up on the example command line.  based on the example filenames that were indicated in the post, the command line should have read

    irun myfile.sv somefile.v

  • You can also use the `begin_keywords compiler directive:

    `begin_keywords "1364-2001"
    module test1 (...);
      output priority; // Valid
      ...
    endmodule
    `end_keywords

    This directive is documented in the SystemVerilog Reference in the documentation.

    Tim

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