Stats

Locked Locked
Replies 3
Subscribers 65
Views 18807
Members are here 0

This discussion has been locked.

You can no longer post new replies to this discussion. If you have a question you can start a new discussion

system verilog compilation with verilog files

I am compiling my system verilog based test bench, the design uses some old modules which have reserve keywords that are not reserved for verilog e.g. program, do, type etc. now when I am compiling it is showing that keywords used, is there any other way to resolve this problem rahter than changing the variable names, can I tell the ncverilog simulator that these are verilog files and hence dont check for the sv keywords in those files.

Regards

Anshuman

Parents

Mickey over 16 years ago

woops... messed up on the example command line. based on the example filenames that were indicated in the post, the command line should have read
irun myfile.sv somefile.v
Cancel
Vote Up 0 Vote Down

Cancel

Reply

Mickey over 16 years ago

woops... messed up on the example command line. based on the example filenames that were indicated in the post, the command line should have read
irun myfile.sv somefile.v
Cancel
Vote Up 0 Vote Down

Cancel

Children

No Data

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.