cannot find urm_defines.svh

Do you have a -incdir option included on your command line that indicates the directory where the urm_defines.svh file is found?

If I add -incdir  option to the command line then I get a set of errors which shows there are errors in declaration of packages along wth other set of errors. for eg:

package urm_util_pkg;
           |
ncvlog: *E,EXPMPA (urm_util_pkg.sv,24|6): expecting the keyword 'module', 'macromodule' or 'primitive'[A.1].

module ab_bus_slave_bfm_m( interface dut_if,
                                                                   |
ncvlog: *E,EXPRPA (ab_bus_slave_bfm.sv,21|43): expecting a right parenthesis (')') [12.1(IEEE)].

import urm_util_pkg::*;
                             |
ncvlog: *E,EXPLPA (ab_bus_slave_bfm.sv,24|19): expecting a left parenthesis ('(') [12.1.2][7.1(IEEE)].

import ab_bus_pkg::*;
                           |
ncvlog: *E,EXPLPA (ab_bus_slave_bfm.sv,25|18): expecting a left parenthesis ('(') [12.1.2][7.1(IEEE)].

 ................

And I think the declaration and code looks fine..I think from the first error it looks like it didnt recognize the keyword "package".. I still have the empty/illegal list of parameters error if i include -incdir option. But the "compilation unit top scope declaration" error goes away.

I have created a urm_defines.svh file in my folder and have included it while compiling along with other .sv files. Now if I dont include -incdir option, then I get only two kinds of errors:For eg:

ncvlog: *E,SVNIMP (abc_parameters.vh,314|20): SystemVerilog construct not yet implemented:  compilation unit top scope declaration.
parameter TJIT_PER         =     100; // tJIT(per)  ps    Period JItter

ncvlog: *E,NULLPP (abc_port.sv,13|39): empty/illegal list of parameters [12.1(IEEE-2001)].
                    SUB_SYSTEM_INSTANCES = 1,

These errors are repeated for all parameters I have for one particular compile-time configuratio. And they are not the same set of parameters in both the files.

Let me know if you need more information. These errors are generated when I use only +sv option in the command line while compiling through ncverilog.

 Thanks,

Rashmikant

Sounds like the problem is that the compiler is not parsing for systemverilog.

if you are using irun, is the file extension of the systemverilog files .sv, or something else?

if you are using ncvlog, try adding -sv to your compile command line.

if you are using ncverilog, try adding +sv to your command line.

let me know if that helps.

Thanks for the quick reply..

I get same set of errors with ncvlog by adding -sv option.

I already have +sv added to the command line and all my systemverilog files have .sv extension. Parameters file have .svh.

I am running this command:

ncverilog +sv $(SIMFILES)

which gives me my previous post's errors..

Thanks,

Rashmikant

it's hard to determine the problem.  Can you send the code you are trying to compile along with the command line you are using?  feel free to send it to my email address (jrodrig@cadence.com)

Hi Rashmikant,

I know this response is very late since the post is from last year, but even i was facing the same problem (SV construct not yet implemented) and so I stumbled upon this post while searching for a solution on the internet.

I am sure you must have figured it out by now, but I would still like to share my experience here for someone else who might be facing the same problem.

It was mainly because of the tool version. I was using 6.2 ius004 which didnt support a few SV constructs that I was using. The problem was solved when i switched to version - 8.2 ius - s017 of the tool.