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cannot find urm_defines.svh

rashmikant

Hi all,

I am a little new to Cadence tools and am using ncverilog for my research purpose.

I am trying to compile system verilog files where I have included urm_defines.svh for some purpose.

But I am getting an error saying it cannot open the include file urm_defines.svh.

 can you give a hint as to what I am missing here? I am sure i am missiing something dumb here.

I am using cadence on my university license. Let me know if you want anyother information.

Btw, i am using ncverilog 05.83-s002 (ius-5.8)

 

Another problem I am facing is that I have made some package files and have used them to build the top-level but I am getting error while importing the package files too and gives an error: urm_util_pkg (and some other user-defined packages too) could not be bound.

Thanks a lot,

Rashmikant

Parents

  • If I add -incdir  option to the command line then I get a set of errors which shows there are errors in declaration of packages along wth other set of errors. for eg:

    package urm_util_pkg;
               |
    ncvlog: *E,EXPMPA (urm_util_pkg.sv,24|6): expecting the keyword 'module', 'macromodule' or 'primitive'[A.1].

    module ab_bus_slave_bfm_m( interface dut_if,
                                                                       |
    ncvlog: *E,EXPRPA (ab_bus_slave_bfm.sv,21|43): expecting a right parenthesis (')') [12.1(IEEE)].

    import urm_util_pkg::*;
                                 |
    ncvlog: *E,EXPLPA (ab_bus_slave_bfm.sv,24|19): expecting a left parenthesis ('(') [12.1.2][7.1(IEEE)].

    import ab_bus_pkg::*;
                               |
    ncvlog: *E,EXPLPA (ab_bus_slave_bfm.sv,25|18): expecting a left parenthesis ('(') [12.1.2][7.1(IEEE)].

     ................

    And I think the declaration and code looks fine..I think from the first error it looks like it didnt recognize the keyword "package".. I still have the empty/illegal list of parameters error if i include -incdir option. But the "compilation unit top scope declaration" error goes away.

     

    I have created a urm_defines.svh file in my folder and have included it while compiling along with other .sv files. Now if I dont include -incdir option, then I get only two kinds of errors:For eg:

    ncvlog: *E,SVNIMP (abc_parameters.vh,314|20): SystemVerilog construct not yet implemented:  compilation unit top scope declaration.
    parameter TJIT_PER         =     100; // tJIT(per)  ps    Period JItter

    ncvlog: *E,NULLPP (abc_port.sv,13|39): empty/illegal list of parameters [12.1(IEEE-2001)].
                        SUB_SYSTEM_INSTANCES = 1,

    These errors are repeated for all parameters I have for one particular compile-time configuratio. And they are not the same set of parameters in both the files.

    Let me know if you need more information. These errors are generated when I use only +sv option in the command line while compiling through ncverilog.

     Thanks,

    Rashmikant

Reply

  • If I add -incdir  option to the command line then I get a set of errors which shows there are errors in declaration of packages along wth other set of errors. for eg:

    package urm_util_pkg;
               |
    ncvlog: *E,EXPMPA (urm_util_pkg.sv,24|6): expecting the keyword 'module', 'macromodule' or 'primitive'[A.1].

    module ab_bus_slave_bfm_m( interface dut_if,
                                                                       |
    ncvlog: *E,EXPRPA (ab_bus_slave_bfm.sv,21|43): expecting a right parenthesis (')') [12.1(IEEE)].

    import urm_util_pkg::*;
                                 |
    ncvlog: *E,EXPLPA (ab_bus_slave_bfm.sv,24|19): expecting a left parenthesis ('(') [12.1.2][7.1(IEEE)].

    import ab_bus_pkg::*;
                               |
    ncvlog: *E,EXPLPA (ab_bus_slave_bfm.sv,25|18): expecting a left parenthesis ('(') [12.1.2][7.1(IEEE)].

     ................

    And I think the declaration and code looks fine..I think from the first error it looks like it didnt recognize the keyword "package".. I still have the empty/illegal list of parameters error if i include -incdir option. But the "compilation unit top scope declaration" error goes away.

     

    I have created a urm_defines.svh file in my folder and have included it while compiling along with other .sv files. Now if I dont include -incdir option, then I get only two kinds of errors:For eg:

    ncvlog: *E,SVNIMP (abc_parameters.vh,314|20): SystemVerilog construct not yet implemented:  compilation unit top scope declaration.
    parameter TJIT_PER         =     100; // tJIT(per)  ps    Period JItter

    ncvlog: *E,NULLPP (abc_port.sv,13|39): empty/illegal list of parameters [12.1(IEEE-2001)].
                        SUB_SYSTEM_INSTANCES = 1,

    These errors are repeated for all parameters I have for one particular compile-time configuratio. And they are not the same set of parameters in both the files.

    Let me know if you need more information. These errors are generated when I use only +sv option in the command line while compiling through ncverilog.

     Thanks,

    Rashmikant

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